Nanomagnet Majority-Gate Adder Circuit for Low-Power Logic
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Solution Overview
Problem
CMOS technology-based logic devices are reaching their physical limits in terms of reliability and power consumption, necessitating the development of alternative nanomagnet-based logic devices that can efficiently perform arithmetic operations like addition with minimal power consumption.
Innovation Solution
The implementation of nanomagnet-based logic devices, specifically a spin orbit torque (SOT) based interlayer exchange coupled nano device, which consists of a first logic device acting as a three-input majority gate and a second logic device acting as a five-input majority gate. These devices are configured to form an adder circuit, where the output of the first logic device is selectively fed to the second logic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS technology-based logic devices are used, then mass adaptation and manufacturing scalability are achieved, but reliability and power consumption reach physical limits
Solution Approach 1:
The patent replaces CMOS electronic logic devices with nanomagnet-based logic devices that use magnetic domain wall motion instead of electrical current flow. The adder circuit uses magnetic domains in nanomagnets to represent logic states (0 and 1), and performs arithmetic operations through magnetic domain wall propagation and interaction, fundamentally substituting electronic mechanisms with magnetic mechanisms to overcome CMOS power and reliability limits
Solution Approach 2:
The patent changes the fundamental operating parameter from electrical voltage/current in CMOS to magnetic domain states in nanomagnets. The adder circuit utilizes magnetic domain wall position and orientation as the state variable, with logic operations performed through controlled domain wall motion and magnetic interaction, representing a parameter change from electrical to magnetic domain control
2Reliability
If nanomagnet-based logic devices are implemented, then power consumption is reduced and reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the adder circuit into distinct functional modules: input nanomagnets for data entry, first and second logic devices for intermediate logic operations, and output nanomagnets for result display. Each module performs a specific function in the addition process, allowing independent optimization and simplifying the overall complex system through functional decomposition
Solution Approach 2:
The patent introduces intermediary nanomagnets and magnetic domain structures that facilitate information transfer and logic operations. The first and second logic devices act as intermediaries between input nanomagnets and output nanomagnets, performing majority logic operations that simplify the direct complexity of nanomagnet interaction while maintaining reliable computation
3Use of energy by moving object
If nanomagnet-based adder circuits are created, then accurate arithmetic operations are achieved with low power consumption, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different structural configurations to different parts of the nanomagnet array: input nanomagnets have specific orientations for data input, logic devices have engineered domain wall pinning sites for stable intermediate states, and output nanomagnets have optimized geometries for clear result detection. This local differentiation of nanomagnet properties allows accurate arithmetic operations while providing tolerance to variations in other manufacturing parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of reliable and efficient nanomagnet-based adder circuits that achieve stable and accurate arithmetic operations with low power consumption, addressing the limitations of CMOS technology.
Implementation Method 1
spin orbit torque (SOT) based interlayer exchange coupled nano device
Implementation Method 2
interlayer exchange coupled nano device
Data Source
AI summary
A system and method for a device is disclosed. A first logic device and a second logic device are provided. Each of the first logic device and the second logic device include at least three inputs and one output, wherein, the output is based on majority of the inputs. The output of the first logic device is selectively fed to the second logic device, wherein, the first logic device and the second logic device together form an adder circuit.