Nanoribbon ESD Diode Junction Layout for Insulated Channels
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Solution Overview
Problem
Existing electrostatic discharge (ESD) diode solutions for nanoribbon and nanowire architectures are not compatible due to the insulating layer separating the source and drain from the semiconductor substrate, making it difficult to form a P-N or P-I-N junction necessary for ESD diodes.
Innovation Solution
Formation of a P-N junction by doping a first region of the nanoribbon with N-type dopants and a second region with P-type dopants, or a P-I-N junction by using intrinsic semiconductor nanoribbons, where the depletion region can be modulated by choosing appropriate work function materials and gate dielectrics to shift or narrow the depletion region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If N-well and P-well configuration is used in semiconductor substrate, then ESD diode can be formed in fin-based devices, but it is not compatible with nanowire and nanoribbon architectures due to insulating layer separation
Solution Approach 1:
The patent transitions from planar P-N junction formation in the substrate to vertical P-N junction formation along the nanoribbon channel. By doping different regions of the suspended nanoribbon structure with opposite polarity dopants, the invention creates a three-dimensional P-N junction that accommodates the insulating layer separation, enabling ESD diode functionality in nanoribbon architectures where traditional substrate-based wells cannot be formed.
2Productivity
If source and drain are separated from semiconductor substrate by insulating layer, then nanoribbon architecture is achieved, but traditional ESD diode formation becomes impossible
Solution Approach 1:
The patent introduces the nanoribbon channel itself as an intermediary structure that carries both the transistor function and the ESD diode function. By forming P-N junctions within the nanoribbon regions adjacent to source and drain, the invention uses the nanoribbon as a mediator to provide ESD protection despite the insulating layer preventing traditional substrate-based well formation. This allows simultaneous achievement of high circuit density and reliable ESD protection.
3Device complexity
If conventional ESD diode structure is used, then simple fabrication process is maintained, but ESD diodes cannot function in nanoribbon devices with insulating layers
Solution Approach 1:
The patent applies local quality by doping specific regions of the nanoribbon structure with different polarity dopants. Rather than requiring a completely new fabrication process, the invention selectively modifies local regions adjacent to source and drain with N-type or P-type dopants, creating functional P-N junctions that enable ESD protection while maintaining compatibility with existing nanoribbon device fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of functional ESD diodes in nanoribbon and nanowire architectures with improved capacitance and reduced leakage, allowing for effective electrostatic discharge management in next-generation semiconductor devices.
Implementation Method 1
doping a first region of the nanoribbon with N-type dopants and a second region with P-type dopants
Implementation Method 2
the gate stack wraps around the full perimeter of the nanowire, enabling fuller depletion in the channel region
Data Source
AI summary
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.