Vertically Stacked Nanosheet Gates With Active Cut Isolation
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Solution Overview
Problem
Existing multi-gate transistors face challenges in scaling and suppressing short channel effects while maintaining effective current control, particularly in integrated circuit devices.
Innovation Solution
A semiconductor device design featuring stacked nanosheets with multiple gate electrodes and isolation layers, including a lower interlayer insulating layer, bottom and upper nanosheets, and gate cuts, which enhance integration and reduce the cell region area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistors are used to suppress short channel effects and improve current control, then device performance is improved, but device complexity increases
Solution Approach 1:
The transistor channel is segmented into multiple discrete nanosheets (first plurality of nanosheets and second plurality of nanosheets) stacked vertically, with isolation layers between them. This segmentation allows each nanosheet to be independently controlled by separate gate electrodes, suppressing short channel effects while maintaining manageable structural complexity through modular design
Solution Approach 2:
The patent transitions from planar 2D channel structures to 3D vertically-stacked nanosheet structures. Multiple nanosheets are arranged in the vertical dimension and controlled by corresponding gate electrodes, enabling effective short channel effect suppression through three-dimensional channel control without proportionally increasing lateral device footprint
2Reliability
If gate length is increased to improve current control, then current control capability is improved, but device area increases
Solution Approach 1:
The patent exploits the vertical dimension by stacking multiple nanosheets and their corresponding gate electrodes vertically. This allows enhanced current control capability through multiple controlled channels without increasing the lateral gate length, thereby reducing the overall cell region area compared to conventional approaches
Solution Approach 2:
Multiple nanosheets and gate electrodes are nested vertically within a compact structure. The first plurality of nanosheets are positioned between the lower interlayer insulating layer and the upper isolation layer, with the second plurality of nanosheets stacked above them, creating a nested vertical arrangement that maximizes current control within minimal footprint
3Productivity
If multiple nanosheets are stacked to increase integration density, then integration is improved, but manufacturing precision requirements increase
Solution Approach 1:
Isolation layers are formed between the first plurality of nanosheets and the second plurality of nanosheets during the manufacturing process. This preliminary structuring establishes precise vertical spacing and positioning early in fabrication, guiding subsequent nanosheet formation and ensuring accurate stacking alignment without requiring extreme precision in later steps
Solution Approach 2:
The upper isolation layer acts as an intermediary structure between the first plurality of nanosheets and the second plurality of nanosheets. This intermediate layer provides a reference plane and physical spacer that facilitates precise positioning of the upper nanosheets relative to the lower nanosheets, reducing the direct precision requirements for nanosheet-to-nanosheet alignment
Data Source
AI summary
A semiconductor device includes a lower interlayer insulating layer, a first plurality of bottom nanosheets, a first plurality of upper nanosheets, an upper isolation layer between the first plurality of bottom nanosheets and the first plurality of upper nanosheets, a first bottom gate electrode on the lower interlayer insulating layer, a first upper gate electrode on an upper surface of the first bottom gate electrode, and a first active cut that extends into each of the first bottom gate electrode and the first plurality of bottom nanosheets in the vertical direction and is on an upper surface of the lower interlayer insulating layer, where the first active cut is spaced apart from the first upper gate electrode in the vertical direction, and where the first active cut at least partially overlaps each of the first upper gate electrode and the first plurality of upper nanosheets in the vertical direction.