Nanosheet IC Backside Contact Layout for Lower Contact Resistance
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Solution Overview
Problem
There is a need for higher capacity and integration in integrated circuit devices while maintaining performance and reliability, which is challenging due to limitations in interconnection structures and backside contact designs.
Innovation Solution
The integrated circuit device incorporates a fin-type active region on a substrate with nanosheets, a gate line surrounding the nanosheets, and a high-concentration doped layer in the source/drain region, along with a backside contact extending from the substrate's lower surface to the source/drain region, enhancing interconnection and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interconnection structures are used, then device complexity is limited, but integration capacity and performance cannot be increased further
Solution Approach 1:
The patent introduces backside contacts that extend from the lower surface of the substrate to the source/drain regions, utilizing the vertical dimension and the backside of the substrate to create additional interconnection paths. This three-dimensional approach to interconnection allows signals to be routed from the backside, reducing congestion on the front side and enabling higher integration capacity without proportionally increasing planar device complexity.
2Reliability
If standard contact designs are used, then manufacturing is simpler, but contact resistance remains high
Solution Approach 1:
The patent implements a high-concentration doped layer specifically in the lower portion of the source/drain regions where the backside contacts make contact. This localized high-doping region creates a low-resistance path at the critical contact interface, reducing contact resistance without requiring high doping throughout the entire source/drain region, thus balancing performance improvement with manufacturing feasibility.
3Productivity
If fin-type active regions with nanosheets are used, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the channel into multiple nanosheet segments stacked vertically on the fin-type active region. Each nanosheet can be independently controlled by the gate line, allowing for multi-threshold voltage devices and improved device performance. The segmentation approach enables better electrical characteristics while the vertical stacking minimizes the lateral footprint, reducing the overall manufacturing precision requirements compared to lateral multi-channel approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases the performance and reliability of integrated circuit devices by improving interconnection efficiency, reducing contact resistance, and enhancing the stress boosting effect on nanosheets, thereby supporting higher integration and capacity.
Implementation Method 1
a high-concentration doped layer disposed in a lower portion of the source/drain region, and having a dopant concentration greater than a dopant concentration of the source/drain region
Implementation Method 2
a backside contact extending from a lower surface of the substrate toward a lower portion of the source/drain region
Implementation Method 3
a gate line disposed on the fin-type active region, the gate line surrounding each of the plurality of nanosheets and extending in a second horizontal direction
Implementation Method 4
a plurality of nanosheets disposed on a top surface of the fin-type active region and separated from the top surface of the fin-type active region
Data Source
AI summary
An integrated circuit device includes a substrate provided with a fin-type active region which is disposed at a first surface of the substrate, a plurality of nanosheets disposed on a top surface of the fin-type active region and separated from the top surface of the fin-type active region, a gate line disposed on the fin-type active region, the gate line surrounding each of the plurality of nanosheets, a source/drain region disposed on the fin-type active region, a sidewall of the source/drain region being adjacent to the gate line and in contact with the plurality of nanosheets, a backside contact extending from a second surface of the substrate toward a lower portion of the source/drain region, and a high-concentration doped layer disposed in the lower portion of the source/drain region. The high-concentration doped layer has a dopant concentration greater than a dopant concentration of the source/drain region.