Nanosheet Transistor Body Contact for Dynamic Threshold Control
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Solution Overview
Problem
Existing nanosheet FETs lack dynamic threshold voltage control, limiting their performance and efficiency.
Innovation Solution
A nanosheet FET structure is fabricated with direct contact between the work function metal and the semiconductor channel layers, allowing for dynamic threshold voltage control through the use of different work function metals for varying voltage thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fully depleted channel is formed by reducing n-type doping concentration in the channel, then short channel effects are suppressed and carrier mobility is improved, but complete depletion of the channel becomes difficult to achieve and threshold voltage control becomes unreliable
Solution Approach 1:
The channel region is segmented into two distinct zones: a first channel region with higher n-type doping concentration and a second channel region with lower n-type doping concentration. This segmentation allows the first region to provide robust threshold voltage control through adequate depletion, while the second region enables complete depletion to suppress short channel effects and enhance carrier mobility.
Solution Approach 2:
Different regions of the channel are assigned different doping concentrations to optimize local functions. The first channel region uses higher doping (1E16 to 1E18 atoms/cm³) for reliable threshold voltage control, while the second channel region uses lower doping (1E14 to 1E16 atoms/cm³) to achieve complete depletion and improve carrier mobility, with each region's properties tailored to its specific functional requirement.
2Productivity
If conventional planar transistor structures are used, then manufacturing is simpler, but device scaling is limited and short channel effects cannot be effectively suppressed
Solution Approach 1:
The transistor structure transitions from a conventional planar configuration to a vertical nanosheet architecture. The channel is formed as a thin nanosheet (5nm to 50nm thick) with source and drain regions positioned above and below, creating a three-dimensional structure that enables effective channel depletion and short channel effect suppression while maintaining manufacturability through established semiconductor processing techniques.
3Speed
If carrier mobility is improved by reducing doping concentration, then transistor switching speed increases, but threshold voltage control becomes unreliable
Solution Approach 1:
The channel is divided into two regions with different doping concentrations to simultaneously optimize carrier mobility and threshold voltage control. The second channel region with lower doping (1E14 to 1E16 atoms/cm³) enables high carrier mobility and fast switching, while the first channel region with higher doping (1E16 to 1E18 atoms/cm³) ensures reliable threshold voltage control through adequate depletion.
Solution Approach 2:
Different sections of the channel are optimized for different functions: the first channel region prioritizes threshold voltage control with higher doping concentration, while the second channel region prioritizes carrier mobility with lower doping concentration. This local optimization allows the transistor to achieve both reliable switching characteristics and high-speed performance.
Data Source
Figure 1
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Figure 4
AI summary
Semiconductor channel layers vertically aligned and stacked, separated by a work function metal and a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal directly contacts a vertical sidewall of each layer. A first set and a second set of semiconductor channel layers vertically aligned and stacked, separated by a work function metal, a gate dielectric partially surrounding and physically separating the work function metal from each, a first portion of the work function metal between the first set and the second set directly contacts a sidewall of each layer. Forming an initial stack of alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked, forming a vertical opening creating a first stack of nanosheet layers and a second stack of nanosheet layers, and exposing vertical side surfaces of the alternating layers of both stacks.