Nanosheet Transistor Bottom Isolation for Leakage-Capacitance Tradeoff
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Solution Overview
Problem
Existing nanosheet transistor devices face a tradeoff between reduced current leakage and increased device capacitance due to the diminishing effect of punch-through layers as gate length scales, and conventional doping methods exacerbate this issue.
Innovation Solution
Implementing a bottom dielectric isolation region formed through a sacrificial layer removal process, followed by epitaxial growth of a semiconductor layer, which reduces leakage current and device capacitance without compromising gate length scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If punch-through implantation is used to reduce leakage, then current leakage is reduced, but device capacitance increases
Solution Approach 1:
The patent extracts and removes the sacrificial layer completely to form a void space, eliminating the need for punch-through implantation and its associated harmful effects. This extraction approach allows the formation of isolation regions without introducing additional doping that would increase capacitance.
Solution Approach 2:
The sacrificial layer acts as an intermediary that is temporarily present during fabrication to enable precise positioning of the isolation region, then removed to achieve the final structure. This intermediary approach allows for controlled isolation formation without requiring punch-through doping.
2Length of moving object
If gate length is scaled to narrow length, then device performance is improved, but leakage current increases due to diminished punch-through layer effect
Solution Approach 1:
The patent transitions from relying on lateral punch-through layer effects (horizontal dimension) to using vertical isolation regions formed by sacrificial layer removal. This dimensional shift allows effective leakage control even as gate length scales to narrow dimensions where traditional punch-through effects diminish.
Solution Approach 2:
The sacrificial layer is positioned and formed in advance before nanosheet fabrication, creating a pre-defined isolation structure that remains effective regardless of subsequent gate length scaling. This preliminary action ensures leakage control is built into the device architecture from the outset.
3Object-generated harmful factors
If increased doping is applied to reduce leakage, then leakage is reduced, but device capacitance increases
Solution Approach 1:
The patent extracts the need for increased doping by using sacrificial layer removal to form isolation regions. This extraction eliminates the tradeoff between doping level and capacitance, achieving leakage control through structural isolation rather than electrical doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves reduced leakage current and device capacitance while enabling gate length scaling, resulting in faster performance and lower energy consumption, with improved source/drain epitaxial quality and integration with conventional semiconductor fabrication processes.
Implementation Method 1
removing the sacrificial layer to form an opening between the nanosheet stack and the substrate
Implementation Method 2
epitaxially growing a semiconductor layer from the sacrificial layer
Implementation Method 3
forming an isolation region by forming an insulating material in the opening
Data Source
AI summary
Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.