Nanosheet Capacitor Vertical Stacking for Density and Leakage
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Solution Overview
Problem
There is a challenge in scaling non-planar device architectures beyond the 7 nm node for semiconductor devices, particularly in integrating on-chip nanosheet-based capacitors with nanosheet CMOS technology, which requires a method to form nanosheet capacitors simultaneously with nanosheet FETs while managing short-channel effects and leakage current.
Innovation Solution
The method involves forming a nanosheet stack with vertically stacked nanosheets, doping exposed portions, and creating gates over channel regions in both nanosheet FETs and capacitors, using a hard mask to remove sidewall spacers and form conductive gates, and integrating interlayer dielectrics and contacts to enhance capacitance and control short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lateral capacitor architectures are used, then manufacturing process is simpler, but device density is lower
Solution Approach 1:
The patent transitions from conventional lateral capacitor architectures to vertical nanosheet-based capacitor structures. The nanosheets are stacked vertically to form multiple capacitor layers, utilizing the vertical dimension to increase device density without proportionally increasing footprint area. This dimensional change enables higher capacitance per unit area while managing the complexity through systematic formation processes.
2Productivity
If nanosheet capacitor structures are implemented, then device density increases, but short-channel effects increase
Solution Approach 1:
The patent segments the channel region into multiple thin nanosheet layers stacked vertically. Each nanosheet forms a separate channel segment with its own gate control, allowing the channel to be fully depleted through the stack. This segmentation enables better electrostatic control and reduces short-channel effects while maintaining high device density through the vertical arrangement of multiple segmented channels.
Solution Approach 2:
The patent implements a nested structure where multiple nanosheet channels are stacked one within another in the vertical dimension, with gates wrapping around each nanosheet. This nesting arrangement allows each channel segment to be independently controlled while collectively achieving high device density, and the wrap-around gates provide enhanced electrostatic control to mitigate short-channel effects.
3Reliability
If wrap-around gate structures are used, then leakage current control improves, but device fabrication complexity increases
Solution Approach 1:
The wrap-around gate structures are formed by nesting conductive gate material around the nanosheet channels in a systematic process. The gates wrap around each nanosheet to provide 360-degree control of the channel, enabling superior leakage current management. The nested formation process, while adding structural complexity, follows a methodical approach that manages fabrication complexity through sequential deposition and patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased device density and performance by fully depleting the channel region, reducing short-channel effects, and managing leakage current and parasitic capacitance, thereby improving the scalability of nanosheet-based semiconductor devices.
Implementation Method 1
A dopant is formed in a channel region of the first and second nanosheets of the second nanosheet stack
Data Source
AI summary
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks.