Nanosheet CMOS Transistors Coplanar Channel Alignment
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Solution Overview
Problem
Current nanosheet fabrication processes result in low-quality structures and topography issues due to offset channel levels in nFET and pFET regions, affecting device performance in semiconductor devices.
Innovation Solution
A method involving the formation of stacks with silicon and silicon germanium layers, where the silicon germanium layers are annealed to convert into high-quality silicon germanium channels, ensuring co-planar alignment and improved quality of nanosheet channels, and the use of dielectric spacers and selective etching to form source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial processes are used to form nanosheet structures, then nanosheet FET devices can be fabricated, but the resulting nanosheet structures have low quality and poor device performance
Solution Approach 1:
The patent changes the material composition parameter by using silicon-germanium-silicon stacked layers instead of conventional epitaxial nanosheet structures. The germanium concentration is varied (e.g., 0%, 10%, 20%) to achieve selective etching and form high-quality nanosheet channels with improved crystal structure and reduced defects compared to epitaxial growth
Solution Approach 2:
The patent employs composite material structures by stacking different semiconductor materials (silicon and silicon germanium) in alternating layers. This composite approach allows selective removal of germanium-containing layers to expose high-quality silicon nanosheet channels, combining the advantages of different materials to achieve superior device performance
2Adaptability or versatility
If silicon germanium sacrificial layers are removed in nFET regions and silicon sacrificial layers are removed in pFET regions, then nanosheet channels can be formed in respective regions, but topography issues arise with channels offset relative to each other
Solution Approach 1:
The patent applies local quality by having different germanium concentration distributions in different regions of the stacked layers. The nanosheet channel regions are designed with specific germanium concentration profiles that enable selective etching while maintaining coplanar alignment, allowing nFET and pFET regions to be formed with properly aligned channels
Solution Approach 2:
The patent performs preliminary action by pre-forming the stacked layers with controlled germanium concentrations before the selective etching step. The germanium-containing layers are strategically positioned and concentrated in specific regions to serve as sacrificial layers, ensuring that when etched, the remaining silicon nanosheet channels will be coplanar and properly aligned across both nFET and pFET regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher quality silicon germanium channels that are co-planar with silicon channels, enhancing device performance and addressing the topography issues in nanosheet FETs, enabling better integration and performance in semiconductor devices.
Implementation Method 1
The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region
Data Source
AI summary
Integrated chips and methods of forming the same include forming a respective stack of sheets in two regions, each stack having first layers and second layers. The second layers are etched away in the first region. The second region is annealed to change the composition of the first layers in the second region by interaction with the second layers in the second region. A gate stack is formed in the first and second region.