Nanosheet Corner Isolation Structure for Lower Gate Parasitic Capacitance
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Solution Overview
Problem
Conventional nanosheet devices face high parasitic capacitance between the metal gate and semiconductor stack due to a thin isolation material, which is exacerbated by the limited thickness of the silicon capping layer during fabrication, leading to performance issues.
Innovation Solution
A semiconductor capping layer made of the same material as the sacrificial semiconductor layer, such as silicon germanium, is used to protect the isolation structure, resulting in a thicker isolation material between the metal gate and semiconductor stack, and a more uniform inner spacer profile, reducing parasitic capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin isolation material is used between the bottom portion of the semiconductor stack and the metal gate, then the device can be fabricated with conventional processes, but high parasitic capacitance occurs between the metal gate and the semiconductor stack
Solution Approach 1:
A corner protection structure is formed at the corner of the isolation structure before forming the metal gate. This preliminary structural preparation ensures that when the metal gate is subsequently formed, it automatically benefits from the enhanced isolation thickness without requiring additional process steps later in fabrication.
Solution Approach 2:
The corner protection structure is specifically placed only at the corner region of the isolation structure, where the problem of thin isolation material is most critical. This localized approach thickens the isolation material precisely where needed to reduce parasitic capacitance, while maintaining conventional process compatibility elsewhere in the device.
2Device complexity
If the silicon capping layer thickness is limited during fabrication, then the fabrication process remains simple, but the isolation material thickness becomes insufficient, causing high parasitic capacitance
Solution Approach 1:
The isolation structure is segmented into two functional parts: the main isolation structure formed by the silicon capping layer, and the corner protection structure formed separately at the corner region. This segmentation allows the corner region to have enhanced isolation thickness while the rest of the device maintains conventional fabrication simplicity.
Solution Approach 2:
The corner protection structure acts as an intermediary element that bridges the gap between the limited silicon capping layer thickness and the required isolation material thickness. It provides the additional isolation thickness needed at the corner without requiring a complete redesign of the capping layer formation process.
3Object-affected harmful factors
If the isolation material thickness is increased to reduce parasitic capacitance, then device performance improves, but the fabrication process becomes more complex
Solution Approach 1:
The corner protection structure is merged with the existing isolation structure formation process. By using the same silicon capping layer material and formation methodology, the corner protection structure integrates seamlessly into the conventional fabrication process without adding significant complexity, while still achieving the goal of increased isolation thickness.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a semiconductor stack including semiconductor layers over a substrate, wherein the semiconductor layers are separated from each other and are stacked up along a direction substantially perpendicular to a top surface of the substrate; an isolation structure around a bottom portion of the semiconductor stack and separating active regions; a metal gate structure over a channel region of the semiconductor stack and wrapping each of the semiconductor layers; a gate spacer over a source/drain (S/D) region of the semiconductor stack and along sidewalls of a top portion of the metal gate structure; and an inner spacer over the S/D region of the semiconductor stack and along sidewalls of lower portions of the metal gate structure and wrapping edge portions of each of the semiconductor layers.


