Nanosheet Gate Stack Dipole Patterning for Multiple Threshold Voltages
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Solution Overview
Problem
The challenge in developing nanosheet-based semiconductor devices is the difficulty in implementing p-type dipole materials like aluminum oxide due to solubility issues with conventional hard mask materials, which complicates the patterning process and limits the ability to achieve multiple threshold voltages in advanced technology nodes.
Innovation Solution
The method involves forming a dipole layer over a high-k gate dielectric layer, recessing it to create a processing window, and using thermal treatment to drive the dipole material into the gate dielectric layer, allowing for the patterning of p-type dipoles and enabling multiple threshold voltage configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If p-type dipole materials like aluminum oxide are used to achieve multiple threshold voltages, then device performance and functionality are improved, but patterning complexity increases due to solubility issues with conventional hard mask materials
Solution Approach 1:
The patent introduces an intermediary material layer (such as a sacrificial layer or alternative hard mask material) that mediates between the p-type dipole material and the patterning process. This intermediary layer protects the dipole material from solubility issues during patterning while still allowing for precise threshold voltage control, thus resolving the contradiction between achieving multiple threshold voltages and maintaining patterning simplicity
Solution Approach 2:
The patent modifies processing parameters such as dipole material thickness, deposition conditions, or etch selectivity ratios to enable successful patterning of p-type dipole materials. By adjusting these parameters, the patent achieves both multiple threshold voltage configurations and manageable patterning complexity, resolving the technical contradiction
2Reliability
If nanosheet-based devices are implemented to improve gate control and reduce leakage, then device performance is improved, but manufacturing difficulty increases due to complex device structures and reduced spacing
Solution Approach 1:
The patent segments the manufacturing process into distinct stages, including separate formation of nanosheets, gate dielectric layers, and dipole material layers. This segmentation allows each component to be optimized independently, making the complex nanosheet-based device structure more manufacturable while preserving the gate control benefits
Solution Approach 2:
The patent performs preliminary actions such as forming sacrificial layers and preparing templates before creating the final nanosheet structure. These preliminary steps simplify subsequent manufacturing operations by pre-establishing the geometric framework, thereby reducing the overall manufacturing difficulty while maintaining device performance
3Adaptability or versatility
If dipole layer recessing is performed to enable patterning, then multiple threshold voltages can be achieved, but processing precision requirements increase due to tight processing windows
Solution Approach 1:
The patent employs dynamic control of the recessing process, adjusting etch conditions and depth in real-time based on feedback from previous steps. This dynamic approach allows precise control over dipole layer removal, achieving multiple threshold voltages while managing the tight processing windows through adaptive process control
Solution Approach 2:
The patent incorporates feedback mechanisms where the results of dipole layer formation and recessing are measured and used to adjust subsequent processing parameters. This feedback loop ensures that multiple threshold voltage configurations are achieved with the required precision, even within tight processing windows
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively patterns p-type dipoles and allows for the achievement of multiple threshold voltages, enhancing the performance and complexity of nanosheet-based semiconductor devices by overcoming solubility limitations and tight processing windows.
Implementation Method 1
conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer
Data Source
AI summary
A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.