Nanosheet FET Source/Drain Buffer Structure for Process Reliability
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Solution Overview
Problem
As IC devices are downscaled, the likelihood of process failures during the manufacture of nanosheet FETs increases, necessitating the development of structures that enhance performance and reliability while ensuring high operating speed and accuracy.
Innovation Solution
The IC device incorporates a fin-type active region with a gate line surrounded by an outer insulating spacer, a source/drain region with a buffer layer and local buffer patterns, and a main body layer, which includes edge buffer portions of varying thickness to stabilize the source/drain regions and prevent damage during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the source/drain region is directly formed adjacent to the gate line during downsscaling, then the device integration density increases, but the likelihood of process failures such as deterioration and short circuits increases
Solution Approach 1:
The buffer layer is formed in advance before the main source/drain region, creating a protective structure that prevents process failures during subsequent manufacturing steps. The buffer layer is deposited conformally on the fin-type active region and selectively removed in non-active areas, establishing a reliable foundation before high-density integration proceeds.
Solution Approach 2:
The buffer layer acts as an intermediary element between the fin-type active region and the main source/drain region. This intermediate structure prevents direct contact that could cause short circuits while enabling controlled doping and electrical connection, thus resolving the contradiction between high integration density and process reliability.
2Ease of manufacture
If the buffer layer has uniform thickness, then the manufacturing process is simpler, but the source/drain region stability near the outer insulating spacer is insufficient
Solution Approach 1:
The buffer layer is designed with non-uniform thickness, featuring a first thickness in the first region (away from outer insulating spacer) and a greater second thickness in the second region (adjacent to outer insulating spacer). This local variation provides enhanced stability where needed while maintaining manufacturability through conformal deposition processes.
3Device complexity
If the edge buffer portion has the same thickness as other buffer portions, then the structure is more symmetric and easier to manufacture, but the reliability at the critical interface with the outer insulating spacer is reduced
Solution Approach 1:
The buffer layer incorporates an edge buffer portion with a third thickness that is greater than both the first and second thicknesses, located specifically at the interface with the outer insulating spacer. This localized thickening enhances interface reliability and prevents process failures at this critical location, while the overall structure remains manufacturable through selective etching and conformal deposition.
Data Source
AI summary
An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region, an outer insulating spacer covering a sidewall of the gate line, a source/drain region on the fin-type active region, wherein the source/drain region includes a buffer layer including a portion in contact with the channel region and a portion in contact with the fin-type active region, the buffer layer including an edge buffer portion having a smaller thickness than other portions thereof at a position adjacent to the outer insulating spacer, a local buffer pattern including a wedge portion, the wedge portion filling a space defined by the edge buffer portion and the outer insulating spacer, and a main body layer in contact with each of the buffer layer and the local buffer pattern.