Nanosheet FET Standard Cell Layout for Off-Current and Variation Control
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Solution Overview
Problem
The increasing off-current due to excessive scaling in nanosheet FETs leads to significant power consumption issues in semiconductor integrated circuit devices, and existing layouts lack effective methods for controlling variations in transistor performance and manufacturing precision.
Innovation Solution
A layout structure for semiconductor integrated circuit devices using nanosheet FETs, where first and second standard cells are arranged side by side with specific gate interconnects, pads, and dummy gate interconnects, allowing for the epitaxial growth of multilayer semiconductor units to form pads between functional and dummy nanosheets, thereby controlling variations in transistor performance and manufacturing precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nanosheet FETs are scaled down to improve integration degree and operating speed, then transistor performance is improved, but off current increases significantly leading to higher power consumption
Solution Approach 1:
The patent segments the channel structure into multiple thin nanosheets stacked vertically, creating a three-dimensional transistor architecture. This segmentation allows for better control of the channel while maintaining compact footprint, addressing the scaling limitations that lead to excessive off-current in planar transistors.
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional nanosheet FETs by stacking multiple channel layers vertically. This dimensional change enables improved gate control and reduced off-current while maintaining small device area, thus improving operating speed without proportionally increasing power consumption.
2Area of stationary object
If standard cells are densely packed to minimize device area, then integration density is improved, but variations in transistor performance and manufacturing precision increase
Solution Approach 1:
The patent introduces dummy nanosheets and dummy gate interconnects at specific locations (particularly at cell boundaries) to create uniform local structures. These dummy elements compensate for edge effects and process variations, reducing transistor performance variations without significantly increasing device area.
Solution Approach 2:
The patent merges functional nanosheets with dummy nanosheets into a unified multilayer semiconductor structure that is epitaxially grown together. This combining approach ensures uniform manufacturing conditions across all nanosheets while maintaining the functional performance of the actual transistors and the compensating effect of the dummy structures.
3Manufacturing precision
If dummy pads are added to control transistor performance variations, then manufacturing precision is improved, but device area increases
Solution Approach 1:
The patent makes the dummy nanosheets and dummy gate interconnects serve multiple functions: they act as placeholders for alignment purposes, provide edge effect compensation, and maintain uniform epitaxial growth conditions. This multi-functionality allows effective control of transistor performance variations without requiring additional dedicated dummy structures that would increase device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and yield of semiconductor integrated circuit devices by reducing variations in transistor performance and manufacturing precision, while also minimizing the device area.
Implementation Method 1
allowing for the epitaxial growth of multilayer semiconductor units to form pads between functional and dummy nanosheets
Data Source
AI summary
A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.