Nanosheet FET Source/Drain Contacts with Pointed Capping Layer

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Solution Overview

Problem

The challenge in semiconductor device manufacturing is to enhance the electrical characteristics of transistors while maintaining reliability and reducing defects in the source/drain regions of integrated circuit devices.

Innovation Solution

The integration of source/drain regions with a source/drain capping layer having a higher doping concentration than the source/drain body layer, and featuring a pointed portion, which is recessed inward from the surface, reduces defects and improves electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a source/drain capping layer with higher doping concentration is introduced, then contact resistivity is reduced and electrical characteristics are improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The source/drain region is divided into multiple functional layers: a source/drain body layer, a source/drain capping layer with higher doping concentration, and a pointed portion. This segmentation allows each layer to perform its specific function - the body layer provides structural integrity while the highly doped capping layer reduces contact resistivity, thereby improving electrical characteristics without requiring a completely redesigned structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The capping layer is introduced only in specific locations where contact resistivity needs to be reduced, rather than uniformly doping the entire source/drain region. The pointed portion is formed only at the contact interface with the gate electrode. This localized approach improves electrical characteristics at critical interfaces while maintaining manufacturing feasibility

Inventive Principle:
Principle #3Local quality

2Reliability

If the source/drain capping layer is recessed inward from the surface, then defects are minimized during epitaxial growth, but the contact area is reduced

Engineering Contradiction:
Improvedefect minimizationVSAvoidcontact area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The capping layer is recessed in the vertical dimension (depth) rather than reducing the horizontal contact area. The pointed portion extends vertically to provide a large contact area with the gate electrode while the recessed structure prevents defects during epitaxial growth. This dimensional transition allows simultaneous optimization of both contact area and defect minimization

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If down-scaling of integrated circuit devices is continued, then device density and integration are improved, but manufacturing precision requirements become more stringent

Engineering Contradiction:
Improvedevice densityVSAvoidfabrication precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The doping concentration of the capping layer is increased to achieve optimal electrical characteristics at smaller dimensions. The pointed portion geometry is optimized with specific radius and height ratios that facilitate precise manufacturing. These parameter optimizations enable continued device down-scaling while maintaining manufacturing feasibility and improving device density

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the electrical characteristics and reliability of the integrated circuit device by reducing contact resistivity and minimizing defects during epitaxial growth, thereby improving overall device performance.

Implementation Method 1

A doping concentration of the source/drain capping layer may be greater than a doping concentration of the source/drain body layer

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 2

This configuration enhances the electrical characteristics and reliability of the integrated circuit device by reducing contact resistivity and minimizing defects during epitaxial growth

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentEP4576987A1Nanosheet fets with source/drain contacts recessed in source/drain regions with a pointed capping layer
Publication Date: 2025.06.25 SAMSUNG ELECTRONICS CO LTD
  • EP4576987A1 patent drawingFigure 1
  • EP4576987A1 patent drawingFigure 2
  • EP4576987A1 patent drawingFigure 3A

AI summary

The present disclosure provides a gate-all-around nanosheet FET integrated circuit device (10) including a plurality of nanosheets (N1-N3), a plurality of device isolation films, a plurality of gate lines (160) disposed on the plurality of device isolation films, a first source/drain region (SD) and a second source/drain region (SD) respectively disposed between the plurality of gate lines (160), wherein each of the first source/drain region and the second source/drain region includes a source/drain barrier layer (132), a source/drain body layer (134) on the source/drain barrier layer, and a source/drain capping layer (136) on the source/drain body layer, wherein a doping concentration of the source/drain capping layer is greater than a doping concentration of the source/drain body layer, the doping concentration of the source/drain body layer is greater than a doping concentration of the source/drain barrier layer. The source/drain capping layer (136) is recessed in the source/drain body layer (134) and includes a pointed portion (PT1) pointing downward, a source/drain contact structure (CA) is also recessed in the source/drain body layer (134) and is in contact with the source/drain capping layer. A method of manufacturing is also disclosed.