Nanosheet GAA Transistors With Selective Gate Oxide Regrowth
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Solution Overview
Problem
In semiconductor fabrication, nanosheet transistors face challenges in withstanding higher voltages due to the larger dimensions of I/O transistors compared to core transistors, which can lead to heat generation and performance issues, particularly in integrated circuits where core transistors operate at lower voltages to manage heat.
Innovation Solution
The implementation of a process that forms gate all around transistors with robust gate dielectrics for I/O transistors without significantly increasing the thickness of gate dielectrics, using a thermal annealing process to regrow the interfacial dielectric layer of I/O transistors while maintaining the same thickness for core transistors, allowing the I/O transistors to withstand higher voltages without compromising the deposition of gate metals between nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric thickness is increased to withstand higher voltages in I/O transistors, then voltage withstanding capability is improved, but the transistor dimensions and heat generation increase
Solution Approach 1:
The patent applies different gate dielectric thicknesses to different transistor types within the same integrated circuit. Specifically, I/O transistors are equipped with thicker gate dielectrics (first thickness) to withstand higher voltages, while core transistors use thinner gate dielectrics (second thickness) to minimize heat generation. This local differentiation resolves the contradiction by optimizing each transistor type for its specific operational requirements rather than using a uniform thickness across all transistors.
2Reliability
If the gate dielectric thickness is increased for I/O transistors, then voltage withstanding capability is improved, but manufacturing complexity increases due to different deposition processes
Solution Approach 1:
The patent segments the gate dielectric formation process into distinct stages: a first gate dielectric layer is deposited uniformly across all transistor regions, followed by a second gate dielectric layer that is selectively deposited only in I/O transistor regions. This segmentation allows different thicknesses to be achieved through a systematic multi-step process rather than attempting to deposit different thicknesses simultaneously, making the manufacturing process more manageable and less complex.
Solution Approach 2:
The patent employs preliminary actions by first depositing the base gate dielectric layer across all regions before selectively adding the additional thickness in I/O regions. Masking layers are prepared and positioned in advance to define where the additional dielectric material should be deposited. This preliminary preparation simplifies the subsequent selective deposition process and reduces manufacturing complexity compared to attempting direct selective deposition without pre-positioned masks.
3Temperature
If the gate dielectric thickness is optimized for core transistors, then heat generation is reduced, but voltage withstanding capability for I/O transistors is insufficient
Solution Approach 1:
The patent implements local quality by providing I/O transistors with enhanced gate dielectric thickness specifically in regions where high voltage withstanding is required, while maintaining thinner gate dielectrics in core transistor regions where heat minimization is the priority. This spatially differentiated approach ensures that each transistor type receives the optimal gate dielectric thickness for its specific functional requirements, resolving the contradiction between heat generation and voltage withstanding capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables I/O transistors to withstand higher voltages while maintaining the performance of core transistors, reducing heat generation and improving the overall efficiency of integrated circuits by ensuring that the gate dielectric thickness is optimized for both types of transistors.
Implementation Method 1
using a thermal annealing process to regrow the interfacial dielectric layer of I/O transistors
Data Source
AI summary
A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer of the I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the core gate all around transistor.