Nanosheet Gate Boundary Isolation for Mixed-Vt FinFET Fabrication
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Solution Overview
Problem
The fabrication of FinFET devices with multiple threshold voltages (Vts) faces challenges due to device dimension shrinkage, particularly in advanced technology nodes like 3 nm and below, where multiple patterning gates (MPGs) experience metal gate material loss and boundary variation issues during wet etching, leading to inconsistent Vt control and increased lateral material loss.
Innovation Solution
A two-step patterning process and a two-step wet etching process are employed to achieve mixed Vts boundary isolation in multiple patterning gates, using a first patterned mask inside the N/P boundary and a second mask outside, with different etching amounts to remove the p-type work function layer in the n-type device region without metal gate material loss, ensuring high Vt in the p-type region and better Vt control and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device feature sizes continue to decrease to achieve higher device density, then device density increases, but fabrication process difficulty increases
Solution Approach 1:
The patent applies segmentation by dividing the gate structure fabrication into multiple discrete steps: forming mandrels, depositing first and second semiconductor layers, selective removal, and sequential deposition of gate dielectric and work function layers. This segmented approach enables precise control of each layer and interface, achieving high device density while maintaining manufacturability through systematic process breakdown.
2Manufacturing precision
If wet etching is used to remove p-type work function layer in n-type region, then Vt control is improved, but metal gate material loss and boundary variation occur
Solution Approach 1:
The patent introduces an intermediary protective layering system where the gate dielectric layer and work function layer are deposited in a specific sequence. The gate dielectric layer acts as a protective barrier during etching operations, preventing metal gate material loss while allowing selective removal of the p-type work function layer in the n-type region. This intermediary structure enables precise Vt control without compromising the metal gate.
Solution Approach 2:
The patent applies local quality by selectively removing the p-type work function layer only in the n-type device region while preserving it in the p-type region. This spatially selective modification allows different threshold voltages to be achieved in different regions of the same device structure, enabling tailored electrical characteristics for specific circuit requirements.
3Power
If multiple patterning gates are fabricated with shrunk dimensions, then device performance is improved, but lateral material loss increases
Solution Approach 1:
The patent applies preliminary action by depositing the gate dielectric layer and work function layer before performing selective removal operations. This preparatory layering establishes protective barriers and defined interfaces in advance, preventing lateral material loss during subsequent etching and processing steps while maintaining the shrunk dimensions necessary for high device performance.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanostructures formed over a substrate, and a first S/D structure formed on sidewall surfaces of the first semiconductor nanostructures. The semiconductor device includes a plurality of second semiconductor nanostructures formed over the substrate, and a second S/D structure formed on sidewall surfaces of the second semiconductor nanostructures. The semiconductor device includes an isolation structure formed between the first S/D structure and the second S/D structure, and the isolation structure has a first sidewall surface in direct contact with the first S/D structure and a second sidewall surface in direct contact with the second S/D structure.