Nanosheet Gate Stack Isolation by Sacrificial Epitaxy Width Control

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Solution Overview

Problem

As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining the integration density and preventing issues such as sacrificial epitaxial layer expansion during shallow trench isolation (STI) heat treatment, which can lead to gate residue and short circuits.

Innovation Solution

The method involves tuning the sacrificial epitaxial layers by etching their sidewalls or adjusting the temperatures used during STI heat treatment to prevent expansion beyond the channel epitaxial layers, thereby maintaining the desired dimensions and preventing short circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but sacrificial epitaxial layer expansion during STI heat treatment occurs leading to gate residue and short circuits

Engineering Contradiction:
Improveintegration densityVSAvoidsacrificial epitaxial layer dimension control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming a mandrel structure with controlled dimensions before depositing the sacrificial epitaxial layer. The mandrel serves as a pre-established template that defines the maximum width of the sacrificial layer, preventing expansion during subsequent STI heat treatment processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent employs parameter changes by carefully controlling the deposition parameters of the sacrificial epitaxial layer to ensure it does not exceed the mandrel width. Additionally, the STI heat treatment parameters are optimized to minimize lateral expansion of the sacrificial layer while still achieving proper isolation formation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the sacrificial epitaxial layer width is increased to maintain process margins, then manufacturing robustness improves, but gate residue and short circuits occur due to expansion beyond channel epitaxial layers

Engineering Contradiction:
Improveprocess robustnessVSAvoidgate residue and short circuits
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The mandrel structure is formed in advance with precisely controlled dimensions that define the maximum acceptable width of the sacrificial epitaxial layer. This preliminary structure provides a physical constraint that prevents the sacrificial layer from expanding beyond safe limits during heat treatment, thereby eliminating gate residue and short circuit issues while maintaining adequate process margins.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel acts as an intermediary structure between the channel epitaxial layer and the sacrificial epitaxial layer. It serves as a template that mediates the width control of the sacrificial layer, ensuring it does not expand beyond the channel layer boundaries while still allowing sufficient process robustness.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures that the sacrificial epitaxial layers do not expand excessively, resulting in a smooth operation definition (OD) shape and reducing the risk of dummy gate etch residue and short circuits between the metal gate and the metal drain.

Implementation Method 1

sacrificial epitaxial layer expansion during shallow trench isolation (STI) heat treatment

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250040214A1Semiconductor device and manufacturing method thereof
Publication Date: 2025.01.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250040214A1 patent drawing
  • US20250040214A1 patent drawing
  • US20250040214A1 patent drawing

AI summary

A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.