Nanosheet Gate Structure for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in increasing density and improving electrical characteristics, particularly in gate-all-around transistors, where the scaling technique struggles with parasitic capacitance and operating speed due to the design of gate electrodes and channel layers.
Innovation Solution
The semiconductor device incorporates a gate electrode that surrounds channel layers with a unique configuration, where the source/drain layer protrudes beyond the gate electrode's end portion, and a gate isolation portion overlaps with the source/drain layer, optimizing the distance between the gate electrode and channel layers to reduce parasitic capacitance and enhance operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate electrode is designed to surround the channel layers in a traditional gate-all-around configuration, then the device density is increased, but the parasitic capacitance increases and operating speed decreases
Solution Approach 1:
The gate electrode is designed with an asymmetric configuration where it surrounds the channel layers on three sides but leaves one side surface of each channel layer exposed. This asymmetric design reduces the gate-to-channel overlap area, thereby decreasing parasitic capacitance while maintaining the high-density benefit of the gate-all-around structure
Solution Approach 2:
The patent applies different structural characteristics to different regions: the gate electrode completely surrounds three sides of the channel layers for maximum control, while deliberately leaving one side surface exposed to minimize parasitic capacitance. This localized differentiation optimizes both density and electrical performance
2Reliability
If the gate electrode completely surrounds the channel layers, then the gate control is improved, but the operating speed is reduced due to increased parasitic capacitance
Solution Approach 1:
The asymmetric gate electrode design provides complete surrounding control on three sides for reliable gate control, while the exposed side surface reduces parasitic capacitance to improve operating speed. This selective surrounding approach optimizes both gate control and speed performance
3Ease of manufacture
If the source/drain layer is positioned symmetrically with respect to the gate electrode, then the manufacturing is simplified, but the parasitic capacitance is maximized
Solution Approach 1:
The source/drain layer is positioned asymmetrically relative to the gate electrode, aligning with the asymmetric gate configuration. This asymmetric positioning reduces the overlap area between the source/drain layer and the gate electrode, thereby minimizing parasitic capacitance while remaining manufacturable
Data Source
AI summary
A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.