Nanosheet Gate Structure for Short-Channel Control in FinFET Scaling
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Solution Overview
Problem
FinFET devices face challenges with gate control over the fin bottom portion, limiting further shrinkage and performance enhancement.
Innovation Solution
The introduction of a Vertically Stacked Multiple Channels horizontal NanoSheet (VS-GAA) device structure, which is fully compatible with FinFET layouts, improves gate control and reduces leakage current through SiGe/Si/SiGe epi-growth and dummy gate processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET device structure is used, then sidewall device width and short channel control are improved, but fin bottom portion gate control is lost
Solution Approach 1:
The patent transitions from the planar FinFET structure to a three-dimensional vertically stacked GAA structure. Multiple channel layers are stacked vertically above the substrate, with the gate electrode wrapping around all sides of each channel layer. This vertical stacking enables the gate to control the channel from top, bottom, and sidewalls simultaneously, achieving complete gate control that was impossible in the FinFET configuration where the gate could only control the sidewalls.
2Productivity
If FinFET device structure is used, then Ion performance is improved, but continue shrunk capability is limited
Solution Approach 1:
The vertically stacked GAA structure enables continued scaling by moving the scaling direction from lateral (planar) to vertical. Multiple thin channel layers can be stacked to achieve the desired effective channel width while maintaining smaller lateral dimensions. This vertical dimension provides additional freedom for scaling that overcomes the limitations of continued FinFET shrinkage.
Solution Approach 2:
The channel is divided into multiple separate thin layers stacked vertically, with gate dielectric and gate electrode between and around each layer. This segmentation into multiple channels allows each layer to be fully controlled by the gate while collectively providing the required current drive capability, enabling scaling that maintains performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The VS-GAA structure enhances gate control, reduces leakage current, and enables more aggressive scaling, addressing the limitations of FinFET devices and improving performance and density.
Implementation Method 1
SiGe/Si/SiGe epi-growth
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate, a well, a plurality of channel sheets, a source/drain region, a contact, a gate electrode, a gate dielectric layer and a spacer. The gate electrode includes at least one inner gate electrode and a top gate electrode. The inner gate electrode is located between the plurality of channel sheets. The top gate electrode is located upon a top of the plurality of channel sheets. The top gate electrode includes a first stage top gate and a second stage top gate. The first stage top gate is stacked on the second stage top gate, and a first gate length of the first stage top gate is less than a second gate length of the second stage top gate. The gate dielectric layer surrounds the gate electrode. The spacer includes at least one inner spacer and a top spacer.