Stacked Nanosheet Gate Spacer Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The high-K dielectric layers on the surfaces of inner spacers in stacked nanosheet field-effect transistors lead to increased parasitic capacitances and degraded device performance due to their thickness.
Innovation Solution
Forming first dielectric layers on the surfaces of inner spacer layers with a lower dielectric constant than the gate dielectric layers, reducing the proportion of gate dielectric layers in the regions between the inner spacer layers, channel layers, and gates, thereby reducing parasitic capacitances and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick high-K dielectric layers are used on inner spacer surfaces, then gate insulation is improved, but parasitic capacitance increases and device performance degrades
Solution Approach 1:
The patent applies different dielectric materials with different properties to different locations: low-K dielectric material is used in the inner spacer region to minimize parasitic capacitance, while high-K dielectric material is used in the gate region to maintain gate insulation. This local differentiation of material properties resolves the contradiction between insulation and parasitic capacitance.
Solution Approach 2:
The inner spacer structure acts as an intermediary element between the gate and source/drain regions. By placing low-K dielectric material in the inner spacer, it mediates the interaction between these components, reducing the parasitic capacitance coupling while the gate dielectric maintains the necessary insulation.
2Object-generated harmful factors
If high-K dielectric layers are reduced in thickness, then parasitic capacitance is reduced, but gate insulation may be compromised
Solution Approach 1:
Different regions are assigned different dielectric materials optimized for their specific functions: the gate dielectric region uses high-K material for insulation, while the inner spacer region uses low-K material for parasitic capacitance reduction. This localized material selection allows both requirements to be satisfied simultaneously.
Solution Approach 2:
The device employs a composite dielectric structure combining high-K and low-K dielectric materials in different spatial locations. This composite approach allows the system to benefit from both high-K material's insulation properties and low-K material's low parasitic capacitance properties.
Data Source
AI summary
A semiconductor structure includes: a substrate; channel structures on the substrate, a channel structure of the channel structures including a plurality of channel layers stacked along a direction perpendicular to a surface of the substrate and a plurality of gate grooves between adjacent channel layers; gate structures spanning the channel structure, the gate structures being also in the plurality of gate grooves; source/drain regions on the substrate on two sides of the gates and the channel layers, the source/drain regions being in contact with sidewalls of a plurality of channel layers; and inner spacer layers between adjacent channel layers, and first dielectric layers between the inner spacer layers and the gate structures, the inner spacer layers being between the source/drain regions and the gate structures.