Nano-sheet and High Voltage Transistor Gate Insulation Formation
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Solution Overview
Problem
The challenge in manufacturing integrated circuits is to develop an efficient process flow for forming nano-sheet devices and high voltage transistor devices on the same substrate, as they require different gate insulation layers due to varying operating voltages, posing a risk of dielectric breakdown.
Innovation Solution
The method involves forming channel semiconductor material, device gate insulation layers, sacrificial gate structures, and replacement gate structures for both nano-sheet and transistor devices, allowing for the efficient fabrication of these devices on the same substrate by defining gate cavities and removing the sacrificial structures to expose and maintain the gate insulation layer appropriately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin gate insulation layer is formed for nano-sheet devices to enable high-speed operation, then switching speed is improved, but dielectric breakdown risk increases when exposed to high voltage
Solution Approach 1:
The patent applies local quality by forming different thicknesses of gate insulation layer in different regions: a first thickness in the nano-sheet device region and a second thickness in the high voltage transistor device region. This allows each device type to have the optimal gate insulation thickness for its specific requirements - thin for high speed in nano-sheet devices, thick for high voltage reliability in transistor devices.
Solution Approach 2:
The patent segments the gate insulation layer formation process into region-specific operations. Different gate insulation layers are formed for different device types on the same substrate, with each layer having tailored thickness characteristics. This segmentation enables simultaneous optimization of high-speed performance and high-voltage reliability in different device regions.
2Reliability
If a thick gate insulation layer is formed for high voltage transistor devices to prevent dielectric breakdown, then reliability is improved, but switching speed decreases
Solution Approach 1:
The patent implements local quality by spatially differentiating the gate insulation layer thickness according to device type. High voltage transistor devices receive a thick gate insulation layer for reliability, while nano-sheet devices receive a thin gate insulation layer for high-speed operation. Each region's gate insulation is locally optimized for its specific functional requirements.
Solution Approach 2:
The manufacturing process is segmented to form separate gate insulation layers for different device types. The first gate insulation layer is formed for nano-sheet devices with thickness optimized for speed, while the second gate insulation layer is formed for high voltage transistor devices with thickness optimized for reliability, preventing dielectric breakdown.
3Adaptability or versatility
If different gate insulation layer thicknesses are formed for different device types on the same substrate, then device performance is optimized, but process complexity increases
Solution Approach 1:
The patent segments the substrate into different device regions and forms separate gate insulation layers for each region. This segmentation allows independent optimization of gate insulation thickness for nano-sheet devices and high voltage transistor devices, achieving superior device performance while managing process complexity through systematic region-based fabrication.
Solution Approach 2:
The patent applies local quality by tailoring the gate insulation layer properties to the specific requirements of each device type on the substrate. This approach enables optimized performance for both high-speed nano-sheet devices and high-voltage transistor devices simultaneously, with the manufacturing process adapted to deliver region-specific quality characteristics.
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, forming channel semiconductor material for a nano-sheet device and a transistor device, forming a device gate insulation layer on both the nano-sheet device and on the transistor device, and forming first and second sacrificial gate structures for the nano-sheet device and the transistor device. In this example, the method also includes removing the sacrificial gate structures so as to define, respectively, first and second gate cavities, wherein the device gate insulation layer is exposed within each of the gate cavities, removing the device gate insulation layer for the transistor device from within the first gate cavity while leaving the device gate insulation layer in position within the second gate cavity, and forming first and second replacement gate structures in the first and second gate cavities, respectively.