Nanosheet Transistors With Inner Spacer Modulation
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Solution Overview
Problem
Conventional methods for patterning work function metals in nanosheet devices face challenges due to limited space between sheets, leading to organic planarization layer pinch-off and difficulties in removing deposited work function metal, which hinders the formation of multiple work function gate stacks necessary for advanced CMOS technology.
Innovation Solution
The use of two sets of inner spacers in nanosheet stacks allows for the formation of multiple threshold voltage devices without metal patterning, where the first set of inner spacers pinches off the work function metal between them and channel layers, enabling high threshold voltage devices, and their removal facilitates low threshold voltage devices by varying work function metal thickness and presence near channel edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional patterning steps are performed after high-k dielectric deposition to pattern work function setting metals, then multiple work function gate stacks can be formed, but organic planarization layer pinch-off occurs in small gaps and the deposited work function metal is difficult to remove
Solution Approach 1:
The patent performs patterning of the semiconductor layers (SiGe and Si) before high-k dielectric deposition by forming inner spacers that define future gate regions. This preliminary patterning eliminates the need for difficult post-deposition metal patterning in narrow gaps, as the spacers are formed when access to the nanosheet stack is still available.
Solution Approach 2:
The inner spacers act as intermediary structures that define the gate regions and control work function metal deposition. By using spacers as a mediating element, the patent avoids direct patterning of work function metals in constrained spaces, allowing work function metals to be deposited conformally and then selectively removed or retained based on spacer presence.
2Area of stationary object
If space between nanosheet stacks is limited, then device footprint is reduced, but patterning of work function metals becomes challenging and organic planarization layer pinch-off occurs
Solution Approach 1:
The patent performs preliminary patterning of semiconductor layers to form inner spacers before high-k dielectric and work function metal deposition. This allows precise definition of gate regions in advance, eliminating the need for high-precision post-deposition patterning in narrow spaces between nanosheet stacks.
Solution Approach 2:
The patent replaces mechanical patterning of work function metals (which requires lithography and etching in narrow gaps) with a deposition-and-removal process using inner spacers as templates. Work function metals are deposited conformally and then selectively removed by dissolving the sacrificial inner spacers, avoiding mechanical patterning challenges in constrained geometries.
3Adaptability or versatility
If inner spacers are used to pinch off work function metal for high threshold voltage devices, then multiple threshold voltages are achieved, but device complexity increases
Solution Approach 1:
The patent achieves multiple threshold voltages by changing the presence or absence of inner spacers, which controls the thickness and distribution of work function metals. This parameter change approach allows multiple threshold voltage devices to be formed using the same deposition process, with differentiation achieved through selective spacer removal rather than complex additional processing.
Solution Approach 2:
The inner spacers serve as temporary, sacrificial structures that are deposited to define gate regions and control work function metal deposition, then completely removed after serving their purpose. These disposable spacers enable complex functionality (multiple threshold voltages) without requiring permanent complex structures in the final device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of multiple work function gate stacks in nanosheet devices without metal patterning, achieving distinct threshold voltages by controlling work function metal thickness and presence, thereby enhancing device variability and mobility.
Implementation Method 1
the first and second silicon germanium layers are etched from exposed lateral sides to remove portions of the first and second silicon germanium layers
Implementation Method 2
the first set of inner spacers pinches off the work function metal between them and channel layers
Implementation Method 3
removing the remaining portions of the first and second silicon germanium layers, leaving a plurality of spaces between the first inner spacers and the silicon layers
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a plurality of first and second silicon germanium layers, and a plurality of silicon layers in a stacked configuration. The stacked configuration includes a repeating arrangement of a silicon layer stacked on an arrangement of at least one of the first and at least two of the second silicon germanium layers. The first and second silicon germanium layers are etched from exposed lateral sides, and plurality of first inner spacers are formed adjacent remaining portions of the first and second silicon germanium layers. Parts of the remaining portions of the second germanium layers are positioned between the first inner spacers and the silicon layers. The method also includes forming a plurality of second inner spacers, and removing the remaining portions of the first and second silicon germanium layers, leaving spaces between the first inner spacers and the silicon layers.