3D-Stacked Nanosheet Inner Spacers Using Segmented SiGe Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing multi-stack semiconductor devices face challenges in forming inner spacers due to difficulties in etching sacrificial SiGe layers with different Ge concentrations, leading to inadequate structural profiles and etch selectivity issues, which affect the formation of cavities for spacer deposition.
Innovation Solution
A multi-stack semiconductor device with an improved isolation structure using a substrate, lower and upper nanosheet transistors, and inner spacers formed from a spacer structure with the same material as the isolation structure, including a gate dielectric layer, and a method of manufacturing that involves forming cavities and depositing inner spacers at the side of the isolation structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single SiGe layer or multiple SiGe layers with different Ge concentrations are used as the isolation structure, then the isolation between lower and upper channel structures is achieved, but it becomes very difficult to etch the sacrificial SiGe layers and isolation SiGe layers to obtain cavities for inner spacer formation
Solution Approach 1:
The isolation structure is segmented into multiple SiGe layers with different Ge concentrations (e.g., 25%, 50%, 75%) arranged in alternating pattern. This segmentation allows selective etching of specific layers based on their Ge concentration, enabling cavity formation while maintaining isolation functionality.
Solution Approach 2:
Different regions of the isolation structure have different Ge concentrations tailored to specific functions: lower Ge concentration layers (e.g., 25%) provide etch selectivity for cavity formation, while higher Ge concentration layers (e.g., 50%, 75%) provide structural support and isolation. This local quality variation resolves the contradiction between etchability and structural integrity.
2Manufacturing precision
If multiple SiGe layers with different Ge concentrations are used to reduce thickness difference, then cavity formation becomes feasible, but etch selectivity is lost and structural profile collapses
Solution Approach 1:
The isolation structure employs alternating SiGe layers with different Ge concentrations where each layer has a specific local quality: lower Ge layers (25%) are designed for selective removal to form cavities, while higher Ge layers (50%, 75%) maintain structural integrity. This local differentiation enables both precise cavity formation and structural stability.
Solution Approach 2:
The isolation structure is a composite of multiple SiGe layers with varying Ge concentrations, combining materials with different etch resistances in a stratified arrangement. This composite structure allows selective etching of specific layers while the remaining layers provide structural support, achieving both manufacturing precision and reliability.
3Ease of manufacture
If SiGe layers with high Ge concentration are etched for inner spacer formation, then cavities are obtained, but low Ge concentration layers are also etched due to lack of etch selectivity
Solution Approach 1:
The alternating SiGe layers have locally optimized Ge concentrations: 25% Ge layers provide high etchability for cavity formation, while 50% and 75% Ge layers provide etch resistance to maintain structural profile. This local quality variation enables selective etching of only the intended layers.
Solution Approach 2:
The Ge concentration parameter is varied across different layers of the isolation structure to create distinct etchability characteristics. By changing the Ge concentration from 25% to 75% across different layers, the patent achieves selective etching where only specific layers are removed while others remain intact for structural support.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Provided is a multi-stack semiconductor device including: a substrate (105); a lower nanosheet transistor including a lower channel structure (110C); a lower gate structure surrounding the lower channel structure and including a gate dielectric layer (IL, HK); lower source/drain regions (170S, 170D) at both ends of the lower channel structure; and at least one lower inner spacer isolating the lower source/drain regions from the lower gate structure; an upper nanosheet transistor, on the lower nanosheet transistor, including an upper channel structure (120C); an upper gate structure surrounding the upper channel structure and including the gate dielectric layer; upper source/drain regions (180S, 180D) at both ends of the upper channel structure; and at least one upper inner spacer isolating the upper source/drain regions from the upper gate structure; and an isolation structure (10I) between the lower and upper channel structures, wherein a spacer structure including a same material forming the lower or upper inner spacer is formed at a side of the isolation structure.