Complementary 3D Nanosheet Matrix FETs Heterogeneous Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in dense heterogeneous integration of stacked transistors with different channel materials due to limitations in etch selectivity and material compatibility, particularly between silicon and SiGe, which affects the performance of p-FETs and limits the integration of III-V materials in standard silicon fabrication processes.
Innovation Solution
A compact stacked nanosheet process is developed, where a first and second nanosheet stack of different channel materials are formed with sacrificial layers, allowing for selective etching and the creation of a gate-all-around structure, enabling the integration of heterogeneous complementary FETs without the need for doping implantation and with improved layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard silicon fabrication processes are used, then manufacturing compatibility is maintained, but integration of heterogeneous channel materials (e.g., III-V materials) is limited
Solution Approach 1:
The patent segments the fabrication process into distinct modules: forming separate nanosheet stacks for different channel materials (silicon-based for nFET, SiGe or III-V for pFET) on the same substrate, then selectively etching and assembling them. This segmentation allows each material type to be processed independently according to its specific requirements while maintaining overall process compatibility
Solution Approach 2:
The patent introduces sacrificial layers as intermediary elements that enable the integration of heterogeneous materials. These sacrificial layers are selectively etched to release and position different channel material nanosheets, acting as temporary mediators that facilitate the assembly of incompatible materials without requiring direct processing of all materials simultaneously
2Reliability
If doping implantation is used to enhance transistor performance, then electrical performance is improved, but crystal damage occurs in the channel material
Solution Approach 1:
The patent replaces the mechanical/chemical process of doping implantation with an alternative approach: forming transistors from intrinsically high-performance channel materials (such as III-V compounds) that achieve superior electrical performance through material properties alone, without requiring ion implantation that would damage the crystal structure
3Productivity
If transistor density is increased through stacking, then productivity is improved, but etch selectivity limitations prevent heterogeneous material integration
Solution Approach 1:
The patent applies local quality by assigning different material compositions to different regions of the device structure: silicon-based channels in nFET regions, SiGe or III-V channels in pFET regions. Each region's material is optimized for its specific function, and sacrificial layers with distinct etch characteristics enable selective processing of each region without affecting others
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the dense integration of stacked transistors with different channel materials, overcoming etch selectivity limitations and enhancing p-FET performance, while avoiding crystal damage and enabling the use of III-V materials for reduced power consumption in nanosheet devices.
Implementation Method 1
removing selectively the first, the second, the third and the fourth sacrificial layer by an etch process that may be selective to the material of the first channel material and the second channel material, and that is not selective to the first, the second, and the third sacrificial layer
Data Source
AI summary
A method for forming heterogeneous complementary FETs using a compact stacked nanosheet process is disclosed. The method comprises forming a first nanosheet stack comprising two layers of a first channel material separated by a second sacrificial layer, forming over the first nanosheet stack an equivalent second nanosheet stack, wherein the first channel material is complementary to the second channel material. The method comprises further forming a first source region and a first drain region, thereby building a first FET, and forming over the first source region and the first drain region a second source region and a second drain region, thereby building a second FET, removing selectively sacrificial layers, and forming a gate stack comprising a gate-all-around structure around all channels.