Stacked Nanosheet Metallic Interface Layer Contact Resistance
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Solution Overview
Problem
The formation of parasitic capacitances between nanosheet channels and source/drain structures in semiconductor devices, along with high source/drain contact resistance due to limited volume of doped semiconductor materials using conventional epitaxial processes, poses challenges in semiconductor device fabrication.
Innovation Solution
The implementation of a metallic interface layer between metal source/drain regions and vertically stacked channel layers, formed by depositing metal-doped germanium oxide and annealing to convert dielectric oxide to a metallic germanide, reduces source/drain contact resistance and forms self-aligned inner spacers using metal-doped insulator materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial processes are used to form doped semiconductor source/drain structures, then the fabrication process is simple, but the source/drain contact resistance is high due to limited volume of doped material
Solution Approach 1:
The patent employs a composite source/drain structure consisting of a doped semiconductor region (e.g., SiGe) combined with a metallic contact region (e.g., tungsten). This composite structure allows the doped semiconductor to provide lattice matching and the metal to provide low contact resistance, thereby resolving the contradiction between simple fabrication and low contact resistance.
Solution Approach 2:
The patent applies local quality by creating a doped extension region with higher doping concentration at the channel interface to reduce contact resistance, while maintaining lower doping in other regions. The metallic contact is also locally applied only at the source/drain contact regions rather than throughout the entire structure.
2Object-generated harmful factors
If inner spacers are formed to reduce parasitic capacitance between channels and source/drain structures, then parasitic capacitance is reduced, but the formation of these structures in various semiconductor materials is challenging
Solution Approach 1:
The patent forms the inner spacer structure before completing the source/drain metallization process. By preliminarily forming the spacer using the doped extension as a template, the subsequent metal deposition and patterning steps become simpler, reducing the overall manufacturing difficulty while achieving parasitic capacitance reduction.
Solution Approach 2:
The doped extension region serves a dual function: it acts as both the electrical contact region and the template for forming the inner spacer structure. This self-service approach eliminates the need for separate spacer formation processes, reducing manufacturing complexity while achieving the desired electrical isolation.
3Reliability
If metal source/drain regions are formed directly on channel layers, then the fabrication process is simplified, but source/drain contact resistance remains high without a metallic interface layer
Solution Approach 1:
The patent introduces a metallic interface layer (e.g., tungsten) as an intermediary between the doped semiconductor source/drain region and the external metal contact. This interface layer serves as a transition that provides both mechanical adhesion and low electrical resistance contact, resolving the contradiction between simplified fabrication and reduced contact resistance.
Solution Approach 2:
The patent changes the electrical parameters at the source/drain interface by introducing a highly conductive metallic layer with low work function, transitioning from a high-resistance semiconductor-semiconductor or semiconductor-metal contact to a low-resistance metal-metal contact through the doped extension and interface layer combination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source/drain contact resistance and enhances the integration of germanium with high-k dielectric materials, improving the performance of germanium-channel field effect transistors by providing a conductive contact and reducing parasitic capacitances.
Implementation Method 1
annealing to convert dielectric oxide to a metallic germanide
Implementation Method 2
convert dielectric oxide to a metallic germanide
Implementation Method 3
forms self-aligned inner spacers using metal-doped insulator materials
Data Source
AI summary
Semiconductor devices include vertically stacked channel layers formed from a semiconductor material. A metallic interface layer is formed between metal source/drain regions and the vertically stacked channel layers. The metallic interface layer includes the semiconductor material and a metal. A gate stack is formed between and around the channel layers.