Nanosheet MIM Capacitor Structure for High-Density Decoupling
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Solution Overview
Problem
Conventional semiconductor device designs face challenges in achieving high capacitance density for MIMCAPs due to the need for additional lithography masks, processing levels, and large areas, which are not feasible as semiconductor chip designs shrink and require more compact decoupling capacitors for improved performance.
Innovation Solution
The method involves forming a nanosheet structure with a metal-insulator-metal capacitor (MIMCAP) device, where a first metal stack wraps around active semiconductor layers and a gate insulator layer is used between the layers, allowing for the formation of high-density MIMCAPs within the nanosheet stack, enabling improved capacitance density without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MIMCAP designs are used in interconnect layers, then decoupling capacitance can be provided, but additional lithography masks and processing levels are required, increasing device complexity
Solution Approach 1:
The patent combines the MIMCAP structure with the nanosheet transistor fabrication process by utilizing the same metal stacks and gate insulator layers for both transistor gate formation and capacitor electrode formation. This merging eliminates the need for separate lithography masks and processing levels that would otherwise be required for independent capacitor fabrication.
Solution Approach 2:
The metal stacks and gate insulator layers serve dual functions: forming the gate structure for nanosheet transistors and simultaneously creating the electrode structure for MIMCAPs. This multi-functionality allows the same structural elements to provide both transistor control and decoupling capacitance without requiring additional dedicated capacitor fabrication steps.
2Reliability
If MIMCAPs are formed in interconnect layers to reduce power rail noise, then decoupling performance is improved, but significant chip area is consumed
Solution Approach 1:
The MIMCAP structure is nested within the nanosheet transistor structure by using the same vertical space and material layers. The capacitor electrodes are formed using the same metal stacks that serve as transistor gates, effectively nesting the capacitor functionality within the transistor footprint rather than requiring separate dedicated capacitor area.
Solution Approach 2:
The patent transitions from planar capacitor layouts to vertical three-dimensional structures by stacking multiple metal-insulator layers vertically. This dimensional change allows capacitance to be increased in the vertical direction rather than requiring lateral expansion of chip area.
3Area of stationary object
If stacked nanosheets are used to reduce device footprint, then area is reduced, but fabrication process complexity increases
Solution Approach 1:
The nanosheet stack structure with alternating semiconductor and sacrificial layers is formed preliminarily before the final gate and capacitor formation steps. This preliminary structuring enables subsequent self-aligned processing where the gate and capacitor electrodes are formed in the same steps, reducing the need for additional alignment-critical lithography steps.
Solution Approach 2:
The fabrication process is designed so that the same processing steps that form the nanosheet transistor gates automatically form the MIMCAP electrodes. The metal deposition and patterning steps serve both transistor and capacitor formation simultaneously, making the process self-service rather than requiring separate dedicated steps for each device type.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a first nanosheet device including a plurality of active semiconductor layers, a first metal stack wrapping around the active semiconductor layers, and a first gate insulator layer between the active semiconductor layers and the first metal stack; and a second nanosheet device including a second metal contact, the first metal stack wrapping around the second metal contact, and a second gate insulator between the second metal contact and the first metal stack.