Stacked Nanosheet MOSFET Channel Doping for Clean Sacrificial Etching
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate, necessitating improved methods for fabricating devices with superior performance and integration while maintaining reliability and electrical characteristics.
Innovation Solution
A semiconductor device design featuring a substrate with active and dummy regions, vertically stacked semiconductor patterns, and a gate electrode with inner electrodes, along with a manufacturing method that includes alternately forming active and sacrificial layers, etching to form recesses, and doping sacrificial layers with dopants of higher atomic weight to enhance etching selectivity and reduce residue formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFETs are scaled down to increase integration, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar MOSFET structures to vertically stacked nanosheet channel structures. Multiple semiconductor patterns are stacked in the vertical dimension to form the channel, allowing increased device density without further lateral scaling. This vertical stacking enables higher integration while maintaining effective channel control and operating characteristics through improved gate wrap-around geometry.
Solution Approach 2:
The channel is segmented into multiple discrete nanosheet structures stacked vertically, with each nanosheet forming an independent conducting path. These segmented channels are separated by insulating layers, allowing individual control and optimization of each sheet's electrical characteristics while collectively achieving high integration density.
2Ease of manufacture
If conventional etching processes are used on sacrificial layers, then manufacturing simplicity is maintained, but residue formation and lattice defects occur
Solution Approach 1:
The patent modifies the chemical composition parameters of the sacrificial layer by doping with high atomic weight elements (such as tungsten, platinum, or gold) at controlled concentrations (1.0×10^19 to 1.0×10^21 atoms/cm³). This parameter change in dopant type and concentration fundamentally alters the etching behavior, enabling selective removal of the sacrificial layer without leaving residues or causing lattice defects in the adjacent semiconductor structures.
Solution Approach 2:
The doped sacrificial layer acts as an intermediary material with tailored etching properties. The high atomic weight dopant serves as a mediator that enhances etching selectivity between the sacrificial layer and surrounding structures, allowing clean removal of the sacrificial layer while protecting the semiconductor patterns from damage or contamination.
3Ease of manufacture
If dopant concentration in the channel is uniformly high, then manufacturing simplicity is maintained, but electrical characteristics deteriorate
Solution Approach 1:
The patent implements non-uniform dopant distribution within the semiconductor patterns, creating regions of different doping concentrations. The third portion (central region) has lower dopant concentration than the first and second portions (edge regions adjacent to inner electrodes). This local quality variation optimizes electrical characteristics by reducing scattering in the channel center while maintaining good contact and field effect at the edges near the gate electrodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and electrical characteristics of semiconductor devices by preventing residue formation and lattice defects, ensuring efficient processing and enhanced performance.
Implementation Method 1
doping a dopant having an atomic weight greater than an atomic weight of silicon (Si) at a dose of 1.0×10^19 atoms/cm2 to 1.0×10^22 atoms/cm2
Implementation Method 2
preventing residue formation and lattice defects
Data Source
AI summary
A semiconductor device includes a substrate including an active pattern, a channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked, on the active pattern, a source/drain pattern connected to the plurality of semiconductor patterns, and a gate electrode including a first inner electrode provided below a first semiconductor pattern among the plurality of semiconductor patterns, on the plurality of semiconductor patterns, and a second inner electrode provided above the first semiconductor pattern, the first semiconductor pattern includes a first portion adjacent to the first inner electrode, a second portion adjacent to the second inner electrode, and a third portion between the first and second portions, the first semiconductor pattern includes a dopant having an atomic weight greater than that of silicon, and a dopant concentration of the third portion is smaller than a dopant concentration of each of the first and second portions.