Nanosheet Multi-Gate Device Merged Dielectric Structure
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in fabricating multi-gate devices, particularly with regards to device fabrication and performance, including issues with inner spacers and metal gate gap-fill in nanowire/nanosheet structures.
Innovation Solution
The proposed solution involves a process flow and device structure that merges interfacial layers (IL) and high-K dielectric (HK) layers between nanowires, eliminating the need for an inner spacer, thereby simplifying the process flow and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inner spacers are used in nanowire/nanosheet structures, then gate control is improved, but defects and voids appear in the source/drain epitaxial layer
Solution Approach 1:
The patent removes the inner spacer component from the device structure entirely. By eliminating the inner spacer, the source of defects and voids in the source/drain epitaxial layer is removed, while gate control is maintained through alternative means such as the merged interfacial and high-K dielectric layers providing adequate electrical isolation and control.
Solution Approach 2:
The patent merges the interfacial layer (IL) and high-K dielectric (HK) layers into a single integrated structure between the nanowires. This merged IL/HK layer combination provides both the electrical isolation function previously requiring inner spacers and maintains gate control, while eliminating the manufacturing defects associated with separate inner spacer structures.
2Reliability
If conventional multi-step processes are used for multi-gate device fabrication, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent combines multiple deposition steps into a single merged IL/HK layer formation process. Instead of separately forming interfacial layers, high-K dielectric layers, and inner spacers in multiple sequential steps, the invention integrates these functions into a unified structure formed through coordinated processing, thereby reducing process complexity while maintaining device performance.
Solution Approach 2:
The merged IL/HK layer structure serves multiple functions simultaneously: it provides electrical isolation between nanowires, maintains gate control, and eliminates the need for separate inner spacer formation. This multi-functional approach reduces the number of process steps required while achieving the same performance objectives.
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.