Nanosheet S/D Bottom Isolation for Leakage and Capacitance Control
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Solution Overview
Problem
Nanosheet transistors face challenges such as current leakage between source/drain and substrate, high parasitic capacitance due to physical connection of S/D features with inner spacers, and less gate control in bottom single gate devices, leading to performance issues.
Innovation Solution
An isolation layer is formed on the bottom surface of the S/D trench to prevent substrate contact, allowing S/D features to be epitaxially grown only from channel semiconductor layers, creating air gaps that reduce leakage and parasitic capacitance, and eliminating the formation of bottom single gate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If S/D features are epitaxially grown from substrate and channel semiconductor layers, then device fabrication is simplified, but current leakage occurs between S/D and substrate
Solution Approach 1:
The patent segments the S/D feature growth by introducing an isolation layer that divides the growth interface into two parts: one from the channel semiconductor layers and another from the substrate. This segmentation prevents direct epitaxial growth from the substrate, eliminating the leakage path while maintaining fabrication simplicity.
Solution Approach 2:
The isolation layer acts as an intermediary between the substrate and the S/D features. It prevents direct contact and epitaxial growth from the substrate, thereby blocking the leakage current path while allowing the S/D features to be properly formed through controlled epitaxial growth from the channel layers only.
2Ease of manufacture
If S/D features physically connect inner spacers surrounding metal gate, then device structure is formed, but high parasitic capacitance occurs between S/D and metal gate
Solution Approach 1:
The patent extracts the harmful physical connection between S/D features and inner spacers by introducing air gaps. These air gaps remove the direct parasitic capacitance coupling while maintaining the necessary structural formation, thereby reducing parasitic capacitance without compromising device assembly.
3Ease of manufacture
If bottom single gate device is formed with bottom portion of metal gate, S/D features and substrate, then device structure is created, but high leakage occurs due to less gate control
Solution Approach 1:
The isolation layer serves as a mediator that prevents the formation of the unwanted bottom single gate device. By blocking the direct interface between substrate and S/D features, it eliminates the leakage-prone bottom gate structure while allowing the desired multi-gate configuration to form from the channel semiconductor layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates bulk leakage current and parasitic capacitance, enhancing the performance of nanosheet transistors by ensuring S/D features are isolated from the substrate and inner spacers, thereby improving device speed and reducing leakage.
Implementation Method 1
the S/D features are epitaxially grown from the substrate and the channel semiconductor layers
Implementation Method 2
the substrate is separated from the S/D feature by a first air gap
Implementation Method 3
a high parasitic capacitance between the S/D features and the metal gate may occur
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.