Nanosheet Source/Drain Isolation for Parasitic Capacitance

Solution Overview

Problem

Nanosheet devices face parasitic capacitance issues due to the source/drain node's connection to the underlying substrate, which affects their performance as CMOS technology scales to smaller dimensions.

Innovation Solution

The formation of an isolation region in the substrate within the source/drain regions is achieved through a method involving the deposition and patterning of gate stacks, spacer formation, substrate recessing, and epitaxial growth of source/drain layers, which reduces parasitic capacitance by creating a recessed region beneath the epitaxial source/drain layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the source/drain node is directly connected to the underlying substrate, then the device structure is simple and manufacturing is easier, but parasitic junction capacitance increases which degrades device performance

Engineering Contradiction:
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful interaction between the source/drain node and substrate by removing a portion of the substrate to form a recessed region. This physical separation eliminates the direct capacitive coupling, thereby reducing parasitic junction capacitance while maintaining manufacturing feasibility through standard recess formation processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a vertical dimension to the source/drain-substrate interface by forming a recessed region. Instead of maintaining a planar contact, the source/drain node is positioned at a different vertical level (z-dimension) relative to the substrate surface, thereby reducing the capacitive coupling area and parasitic effects.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If an isolation region is formed by recessing the substrate, then parasitic capacitance is reduced, but the manufacturing process becomes more complex

Engineering Contradiction:
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the substrate into different regions: a recessed region beneath the source/drain node and a non-recessed region elsewhere. This segmentation allows the isolation function to be localized only where needed (under the source/drain), avoiding unnecessary complexity in the entire device structure while effectively reducing parasitic capacitance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary material (such as dielectric material or sacrificial material) that fills the recessed region or is used during the recess formation process. This intermediary enables the creation of the isolated structure through standard deposition and etching processes, making the manufacturing complexity manageable while achieving the parasitic reduction goal.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes parasitic junction capacitance, enhancing the performance and efficiency of nanosheet devices by reducing unwanted electrical interactions between the source/drain and the substrate, thereby improving the overall functionality of CMOS devices.

Implementation Method 1

growing by an epitaxial process an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9515138B1Structure and method to minimize junction capacitance in nano sheets
Publication Date: 2016.12.06
  • US9515138B1 patent drawing
  • US9515138B1 patent drawing
  • US9515138B1 patent drawing

AI summary

A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region.