Nanosheet Transistor Epitaxial Structure for Short-Channel Reliability
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Solution Overview
Problem
The reduction in transistor size in semiconductor devices leads to a short-channel effect, which existing technologies have not adequately addressed, particularly in fin field effect transistors and gate-all-around field effect transistors, affecting manufacturing yield and reliability.
Innovation Solution
A semiconductor device design featuring a substrate with a gate structure surrounding channel layers, where the source/drain regions include epitaxial layers with specific crystal planes and compositions, ensuring a constant thickness and preventing etching errors during the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to improve integration degree, then integration degree is improved, but short-channel effect occurs worsening device reliability
Solution Approach 1:
The patent transitions from planar transistors to vertically stacked nanosheet transistors, utilizing the third dimension (vertical stacking of multiple channel layers) to increase integration density while maintaining adequate channel control and mitigating short-channel effects through the gate-all-around structure
Solution Approach 2:
The gate structure completely surrounds each nanosheet channel layer in a nested configuration, with the gate electrode wrapping around the channel from all sides, providing enhanced electrostatic control and suppressing short-channel effects in the scaled-down device
2Ease of manufacture
If epitaxial layer thickness is not controlled precisely, then manufacturing process is simplified, but etching errors occur worsening manufacturing yield
Solution Approach 1:
The patent specifies precise epitaxial layer thickness parameters (first thickness in the first direction and second thickness in the second direction) and controls crystal plane orientations ((111) or (100) planes), using these parameter specifications to guide the epitaxial growth process and ensure consistent etching behavior
Solution Approach 2:
The epitaxial layers are formed with predetermined thicknesses and crystal plane orientations before subsequent etching and patterning steps, establishing a controlled foundation that prevents etching errors and ensures manufacturing yield
3Ease of manufacture
If crystal plane alignment is not precise, then manufacturing process is easier, but shorts between gate electrode and source/drain regions occur worsening device reliability
Solution Approach 1:
The patent specifies precise crystal plane orientation parameters ((111) or (100) planes for the side surfaces of channel layers) to control the epitaxial growth direction and ensure proper alignment between the gate electrode and source/drain regions, preventing short circuits
Solution Approach 2:
The patent replaces mechanical alignment methods with crystallographic alignment, using the inherent crystal plane orientations ((111) or (100) planes) of the semiconductor material to automatically ensure proper geometric relationships between components, eliminating the need for complex mechanical alignment processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances manufacturing yield and reliability by maintaining a constant epitaxial layer thickness, preventing shorts between the gate electrode and source/drain regions, and ensuring precise crystal plane alignment, thus improving the semiconductor device's performance.
Implementation Method 1
a first epitaxial layer connected to each of side surfaces of the plurality of channel layers
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: an active pattern extending in a first direction on a substrate; channel layers arranged on the active pattern; a gate structure crossing the active pattern, and surrounding the plurality of channel layers, the gate structure extending in a second direction that crosses the first direction; and source/drain regions provided on the active pattern on both sides of the gate structure, and including a first epitaxial layer connected to each of side surfaces of the channel layers, and a second epitaxial layer provided on the first epitaxial layer and having a composition different from that of the first epitaxial layer. Each of the side surfaces of the plurality of channel layers has a crystal plane of (111) or (100). The first epitaxial layer extends in the second direction and has a first thickness in the first direction that is substantially constant.