Nanosheet Transistor Isolation Structure for Stronger Gate Control
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Solution Overview
Problem
As transistor dimensions are scaled down, nanosheet FETs face challenges in further improvements for higher device density, performance, and lower costs, requiring innovative manufacturing processes to maintain effective gate control and reduce short-channel effects.
Innovation Solution
The process involves forming a stack of semiconductor layers over a substrate, creating fin structures, and forming isolation structures in a sacrificial gate material before defining the sacrificial gate structures, which allows for the formation of gate electrode layers that surround the nanosheet channels, enabling better control and minimizing gate height demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then higher device density is achieved, but gate control deteriorates and short-channel effects increase
Solution Approach 1:
The patent transitions from planar 2D gate control to three-dimensional wrap-around gate structures (triple-gate and multi-gate configurations) that surround the channel in multiple dimensions. This dimensional change allows the gate electrode to control the channel from top, bottom, and sides simultaneously, providing superior electrostatic control at scaled dimensions while maintaining high device density through vertical stacking of multiple channels.
Solution Approach 2:
The patent implements nested gate structures where inner gate electrodes are positioned within recesses of outer gate electrodes, creating concentric multi-gate configurations around the channel. This nesting approach maximizes gate control coverage while minimizing the lateral footprint, enabling high device density without compromising gate control effectiveness.
2Reliability
If nanosheet FET structures are implemented to improve gate control, then gate control and short-channel effect reduction are achieved, but fabrication complexity increases
Solution Approach 1:
The patent divides the channel region into multiple discrete nanosheets separated by sacrificial layers, allowing independent formation and control of each channel. The gate structure is segmented into multiple gate electrodes (inner and outer gates) that can be independently formed and biased, providing flexible control while simplifying the overall fabrication through modular construction approaches.
Solution Approach 2:
The patent uses sacrificial layers (such as silicon oxide or silicon nitride) as intermediary materials during fabrication to define and separate nanosheet channels. These sacrificial layers are deposited, patterned, and etched to create the nanosheet structure, then selectively removed to release individual nanosheets. This intermediary approach simplifies the complex task of creating suspended nanosheet structures with precise spacing.
3Reliability
If triple-gate or multi-gate structures are used to reduce short-channel effects, then short-channel effects are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps where sacrificial layers are deposited and patterned before forming the gate electrodes. This preliminary structure defines the precise locations where nanosheets will be released and where gate electrodes will be positioned, ensuring accurate alignment without requiring complex real-time alignment procedures. The sacrificial layers act as templates that guide subsequent fabrication steps.
Solution Approach 2:
The patent utilizes self-aligned fabrication techniques where previously formed structures serve as alignment references for subsequent steps. For example, the outer gate electrode formation uses the inner gate structure as an alignment reference, and the release hole patterning uses the gate electrodes as references. This self-service approach automatically ensures precise alignment without requiring additional alignment equipment or procedures.
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a plurality of semiconductor layers vertically stacked over a substrate, a source/drain feature in contact with each of the plurality of the semiconductor layers, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a source/drain contact disposed above the source/drain feature, a gate spacer disposed between the gate electrode layer and the source/drain contact, and an isolation structure extending through the gate electrode layer. The isolation structure includes a first portion having three sides covered by the gate electrode layer, the first portion having a top surface at a first elevation, and a second portion extended outwardly from the first portion, the second portion having a top surface at a second elevation that is lower than the first elevation.