Nanosheet Transistor Inner Spacers for Source-Drain Isolation

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Solution Overview

Problem

The challenge in fabricating nanosheet FET devices lies in isolating source and drain regions during etching processes, particularly at production nodes below 5 nm, where degradation of these regions can occur due to the removal of sacrificial nanosheet layers.

Innovation Solution

The formation of a stacked nanosheet structure with alternating sacrificial and channel nanosheets, accompanied by the creation of inner spacers and an epitaxially grown isolation layer, which isolates the source and drain regions from the etching process, preventing degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If sacrificial nanosheets are removed through etching process, then channel nanosheets are released and device structure is formed, but source and drain regions are degraded

Engineering Contradiction:
Improvenanosheet structure formationVSAvoidsource and drain region integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

An isolation layer is introduced as an intermediary protective barrier between the etching process and the source/drain regions. This isolation layer selectively protects the source and drain regions during the removal of sacrificial nanosheets, preventing etchant damage while allowing the sacrificial material to be removed. The isolation layer acts as a mediator that enables the etching process to proceed without harming sensitive regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The isolation layer is formed before the etching process that removes sacrificial nanosheets. This preliminary protective action ensures that when the etching occurs, the source and drain regions are already shielded. The protective structure is prepared in advance, allowing the subsequent sacrificial nanosheet removal to proceed without degrading the source and drain regions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If inner spacers and isolation layer are formed to protect source and drain regions, then source and drain regions are isolated from etching, but device structure complexity increases

Engineering Contradiction:
Improvesource and drain region protectionVSAvoidnanosheet device structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective structure is segmented into distinct functional components: inner spacers that provide local protection adjacent to channel nanosheets, and an isolation layer that provides broader protection to source and drain regions. This segmentation allows each component to perform its specific protective function independently, making the overall protection system more manageable and less complex than a monolithic protective structure would be.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively isolates the source and drain regions, minimizing their degradation during the etching of sacrificial nanosheets, thus ensuring the integrity of the nanosheet transistor structure.

Implementation Method 1

An isolation layer is epitaxially grown within the gaps defined between the spacers and adjacent outer surface regions of the channel nanosheets

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11183561B2Nanosheet transistor with inner spacers
Publication Date: 2021.11.23 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11183561B2 patent drawing
  • US11183561B2 patent drawing
  • US11183561B2 patent drawing

AI summary

A method includes forming a stacked nanosheet structure on a semiconductor substrate. The stacked nanosheet structure includes a plurality of alternating sacrificial nanosheets and channel nanosheets. The method further includes forming a dummy gate structure about the stacked nanosheet structure. The method also includes removing outer surface regions of the sacrificial nanosheets to define an at least partial recess at each outer surface region and forming an inner spacer within each of the at least partial recesses. The method also includes forming an isolation layer adjacent at least outer surface regions of at least the channel nanosheets. The method further includes forming a source region and a drain region about the stacked nanosheet structure. The method also includes removing the sacrificial nanosheets through an etching process whereby the isolation layer and the inner spacers isolates the source and drain regions from the etching process.