Nanosheet Transistor Stack Structure for Reducing Stacking Faults
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Solution Overview
Problem
As semiconductor devices continue to downscale, there is a need to prevent process defects such as stacking faults in field-effect transistors, while also improving the electrical characteristics and reliability of these devices.
Innovation Solution
The semiconductor device incorporates a first and second transistor with channel regions formed by nanosheets, a dummy layer, a protective layer with an indented portion, and a spacer. This configuration aims to reduce the occurrence of stacking faults and enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are downscaled to increase integration degree, then device density and miniaturization are improved, but process defects such as stacking faults increase
Solution Approach 1:
A protective layer is introduced as an intermediary structure between the first and second transistors. This protective layer includes a first portion extending over the first transistor and a second portion extending over the second transistor, with a second depth greater than a first depth. The protective layer acts as a mediator that prevents direct interaction between the transistors that could cause stacking faults, while still allowing the devices to be closely integrated.
Solution Approach 2:
The protective layer exhibits local quality variations through its different depths over different transistors. The first portion has a first depth over the first transistor, while the second portion has a second depth over the second transistor, with the second depth being greater than the first depth. This localized depth variation provides targeted protection where needed while maintaining device performance in other areas.
2Volume of moving object
If device size is reduced to improve miniaturization, then device density is improved, but operation accuracy may deteriorate
Solution Approach 1:
The protective layer extends in the vertical dimension with varying depths over different transistors. By utilizing the vertical dimension rather than only horizontal scaling, the device achieves miniaturization in the planar area while maintaining sufficient separation and protection in the vertical dimension to preserve operation accuracy.
3Reliability
If new transistor structures are introduced to eliminate process defects, then reliability is improved, but device complexity increases
Solution Approach 1:
The protective layer serves multiple functions simultaneously: it provides physical separation between transistors to prevent stacking faults, acts as a protective barrier during manufacturing processes, and maintains the structural integrity of the device. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.
Data Source
AI summary
A semiconductor device of the technical idea of the inventive concept includes a first transistor including a first channel region extending in a first direction and a first source/drain region contacting the first channel region, a second transistor including a second channel region on the first transistor and spaced apart from the first transistor in a second direction perpendicular to the first direction and extending in the first direction and a second source/drain region contacting the second channel region, a dummy layer beneath the first transistor, a protective layer beneath the dummy layer and including an indented portion that is indented in the first direction, and a spacer on the indented portion.