Nanosheet Transistor Wrap-Around Bottom Dielectric Isolation

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Solution Overview

Problem

Existing nanosheet FET fabrication processes face challenges in achieving effective bottom dielectric isolation between the substrate and the source/drain regions and the gate, leading to unwanted parasitic capacitance due to unintentional recess in shallow trench isolation regions.

Innovation Solution

A wrap-around bottom dielectric isolation structure is formed by depositing an isolation material in the space occupied by a sacrificial structure, creating a central region and legs that extend around the substrate, ensuring the high-k metal gate stack does not contact the substrate, thereby minimizing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If shallow trench isolation regions are formed in conventional nanosheet FET fabrication, then substrate isolation is provided, but unintentional recess occurs leading to increased parasitic capacitance

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidisolation region depth control
Core Design Contradiction:
Object-affected harmful factorsVSManufacturing precision

Solution Approach 1:

The isolation structure transitions from a planar shallow trench isolation to a three-dimensional wrap-around configuration that extends laterally around the nanosheet stack. The legs of the isolation structure wrap around the substrate edges, providing isolation in multiple spatial dimensions rather than just a single planar layer, thereby eliminating parasitic capacitance pathways without relying on precise depth control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The sacrificial structure is formed beforehand in a wrap-around configuration, and the isolation material is deposited to follow this pre-established pattern. This preliminary positioning of the sacrificial structure ensures that the final isolation material automatically achieves the desired wrap-around geometry and depth, eliminating the need for subsequent precise depth adjustment steps.

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If wrap-around bottom dielectric isolation structure is formed, then parasitic capacitance is reduced, but fabrication process complexity increases

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidisolation structure geometry
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

A sacrificial structure serves as an intermediary template during fabrication. This sacrificial structure is formed in the desired wrap-around configuration, and isolation material is deposited conformally around it. After isolation material deposition, the sacrificial structure is removed, leaving the complex wrap-around isolation geometry without requiring direct formation of the complex shape, thereby simplifying the fabrication process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The complex wrap-around geometry is preliminarily established by the sacrificial structure before isolation material deposition. This preliminary action allows the isolation material to simply conform to the pre-defined geometry, avoiding the need for complex direct patterning or etching steps to create the wrap-around shape, thus reducing overall process complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces parasitic capacitance and enlarges the process window for shallow trench isolation regions, accommodating unintentional recess variations and improving AC performance of nanosheet FETs.

Implementation Method 1

an isolation material is deposited in a space that was occupied by the sacrificial structure

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

an isolation material is deposited in a space that was occupied by the sacrificial structure

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS11189713B2Nanosheet transistor having wrap-around bottom isolation
Publication Date: 2021.11.30 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11189713B2 patent drawing
  • US11189713B2 patent drawing
  • US11189713B2 patent drawing

AI summary

Embodiments of the invention are directed to a method of performing fabrication operations to form a nanosheet field effect transistor (FET) device. The fabrication operations include forming a sacrificial structure over a substrate, wherein the sacrificial structure includes a central region, a first leg at a first end of the central region, and a second leg at a second end of the central region. A nanosheet stack is formed over the central region. An isolation material is deposited within a space that was occupied by the sacrificial structure to form a wrap-around bottom dielectric isolation (BDI) structure having a BDI central region, a first BDI leg at a first end of the BDI central region, and a second BDI leg at a second end of the BDI central region.