Nanosheet Gate Work Function Layout for Dense Multi-Vt Transistors
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Solution Overview
Problem
The integration density of nanosheet field effect transistors (NSFETs) is limited by the vertical spacing between nanosheet channel structures, which restricts the effectiveness of doping and dipole engineering, and increases the device height, compromising storage capacity in memory devices like SRAM.
Innovation Solution
A method is developed to form NSFETs with different gate electrode structures laterally beside each other without sacrificing device density, using dummy masking structures to prevent over-etching and allow for multiple gate electrode layers, enabling varied threshold voltages without increasing device height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical spacing between nanosheet channel structures is reduced to increase integration density, then device density improves, but doping effectiveness and dipole engineering are restricted
Solution Approach 1:
The patent transitions from vertical stacking of nanosheet channels to lateral arrangement of multiple nanosheet channels on the same substrate plane. This dimensional change allows sufficient vertical spacing for effective doping and dipole engineering while maintaining high integration density through lateral packing of multiple channel structures.
Solution Approach 2:
The invention divides the single vertical stack configuration into multiple separate nanosheet channel structures arranged laterally on the substrate. Each nanosheet channel can be independently doped and engineered with dipoles, while the collective array maintains high device density through optimized lateral spacing and arrangement.
2Reliability
If multiple gate electrode layers are formed to achieve desired work function, then gate control improves, but device height increases
Solution Approach 1:
Instead of increasing device height by stacking multiple gate electrode layers vertically, the patent forms multiple nanosheet channel structures laterally beside each other on the same substrate plane. Each channel structure has its own gate electrode, allowing independent work function optimization through material selection rather than through vertical layering, thus maintaining compact device height.
Solution Approach 2:
The invention applies different gate electrode materials or configurations to different local regions (individual nanosheet channels) to achieve desired work functions and threshold voltages. This local optimization allows each channel to be independently tuned for specific electrical characteristics without requiring multiple universal gate layers that would increase overall device height.
3Adaptability or versatility
If NSFETs with different threshold voltages are formed on the same substrate, then device versatility improves, but manufacturing complexity increases
Solution Approach 1:
The patent implements different gate electrode materials, doping configurations, or dimensional parameters for different nanosheet channel structures located at different positions on the substrate. This local differentiation enables each channel to have customized threshold voltages tailored to specific circuit requirements, while the overall manufacturing process remains systematic through standardized fabrication techniques applied to replicated channel structures.
Solution Approach 2:
The invention achieves varied threshold voltages by changing key parameters such as gate electrode material composition, channel width, channel length, or doping concentration in different nanosheet channels. These parameter variations allow continuous tuning of electrical characteristics across the device array without requiring fundamentally different fabrication processes, thus managing manufacturing complexity while maximizing versatility.
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first transistor having a first conductivity type arranged over a substrate. The first transistor includes a first gate electrode layer having a first work function and extending from a first source/drain region to a second source/drain region, and a first channel structure embedded in the first gate electrode layer and extending from the first source/drain region to the second source/drain region. A second transistor having the first conductivity type is arranged laterally beside the first transistor. The second transistor includes a second gate electrode layer having a second work function that is different than the first work function and extending from a third source/drain region to a fourth source/drain region. A second channel structure is embedded in the second gate electrode layer and extends from the third source/drain region to the fourth source/drain region.