Nanostructure FET Gate Recess Etching for Symmetric Backside Vias
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Solution Overview
Problem
The challenge of maintaining symmetric sidewall profiles during the formation of openings in semiconductor devices, particularly in nanostructure field-effect transistors, arises due to asymmetric scattering of etchants, which can interfere with the formation of backside vias in power rail applications.
Innovation Solution
The use of an isotropic etching process to completely remove the segment of the gate structure underlying the cut pattern, followed by an anisotropic etching process to form the opening, ensures a symmetric sidewall profile, thereby facilitating the formation of symmetric backside vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If anisotropic etching is used to form openings, then etching speed and selectivity are improved, but asymmetric sidewall profiles are created due to asymmetric scattering of etchants
Solution Approach 1:
The patent applies preliminary action by performing an isotropic etch before the anisotropic etch. This preliminary isotropic etch removes the gate structure segment and creates a symmetric foundation, ensuring that subsequent anisotropic etching produces symmetric sidewalls. The preliminary action addresses the symmetry issue before the high-speed anisotropic etching begins.
Solution Approach 2:
The patent changes the etching parameters by switching from anisotropic etching (which causes asymmetric scattering) to isotropic etching (which provides uniform etching in all directions). This parameter change in etching directionality and chemistry allows symmetric sidewall formation while maintaining etching effectiveness.
2Manufacturing precision
If isotropic etching is used to remove gate structure, then symmetric sidewall profile is achieved, but additional process steps are required
Solution Approach 1:
The isotropic etch is positioned as a preliminary step that performs multiple functions: removing the gate structure segment and establishing symmetric sidewalls for subsequent processing. By combining these functions in one step, the patent minimizes the need for additional separate process steps despite the added complexity.
3Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but asymmetric scattering effects become more pronounced
Solution Approach 1:
The patent changes the fundamental parameter of etching directionality from anisotropic to isotropic for the gate removal step. This parameter change ensures that even at reduced minimum feature sizes, the etching remains uniform and symmetric, preventing asymmetric scattering effects from degrading sidewall profile control in high-density integration scenarios.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses the issue of asymmetric sidewall profiles, ensuring consistent and reliable formation of backside vias, enhancing the manufacturing process of nanostructure field-effect transistors.
Implementation Method 1
an isotropic etching process is performed to remove the segment of the gate structure
Implementation Method 2
an anisotropic etching process is performed to form the opening
Data Source
AI summary
A method of forming a semiconductor device includes: forming a gate structure over a fin; forming an interlayer dielectric (ILD) layer over the fin around the gate structure; forming a first dielectric plug and a second dielectric plug in the gate structure on opposing sides of the fin, where the first and second dielectric plugs cut the gate structure into a plurality of discrete segments; forming a patterned mask layer over the ILD layer, where an opening of the patterned mask layer exposes a segment of the gate structure interposed between the first and second dielectric plugs; etching, using the patterned mask layer as an etching mask, the segment of the gate structure using an isotropic etching process to form a recess in the gate structure; extending the recess into the fin by performing an anisotropic etching process; and after extending the recess, filling the recess with a dielectric material.