Nanostructure FET Interposer Replacement for Strain Engineering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) manufacturing is to manage the increasing complexity and strain in nanostructure field-effect transistors (FETs) while maintaining device performance and efficiency, particularly in n-type (NFET) and p-type (PFET) FETs.
Innovation Solution
The solution involves replacing SiGe interposers in NFET device regions with substantially pure Ge to enhance tensile strain and in PFET device regions with dielectric materials to change tensile strain into neutral or compressive strain, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If SiGe interposers are used in NFET device regions, then device performance is maintained, but tensile strain is insufficient
Solution Approach 1:
The patent changes the material composition parameter of the interposer layer by replacing SiGe (silicon germanium) with substantially pure Ge (germanium). This material substitution increases the lattice mismatch with silicon channels, thereby enhancing tensile strain in NFET device regions while maintaining device performance through controlled epitaxial growth processes.
Solution Approach 2:
The patent applies different interposer materials to different device regions: substantially pure Ge is used in NFET regions to maximize tensile strain, while dielectric materials are used in PFET regions to achieve neutral or compressive strain. This localized material selection optimizes strain characteristics for each transistor type without compromising overall device performance.
2Stress or pressure
If SiGe interposers are replaced with substantially pure Ge in NFET regions, then tensile strain is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the interposer structure into region-specific materials: NFET regions receive substantially pure Ge interposers for enhanced tensile strain, while PFET regions receive dielectric interposers for neutral/compressive strain. This segmentation allows independent optimization of strain characteristics for each device type while managing manufacturing complexity through targeted material deposition.
Solution Approach 2:
The patent introduces an intermediary process step where the interposer layer is selectively replaced after channel formation but before source/drain epitaxy. This intermediary replacement step enables precise control over strain introduction timing, allowing the substantially pure Ge interposer to be deposited only in NFET regions where enhanced tensile strain is needed, thereby managing manufacturing complexity.
3Stress or pressure
If SiGe interposers are replaced with dielectric materials in PFET device regions, then compressive strain is achieved, but device performance may be degraded
Solution Approach 1:
The patent changes the interposer material parameter in PFET regions from SiGe to dielectric materials. This substitution transforms the strain characteristic from tensile (provided by SiGe) to neutral or compressive (provided by dielectric materials), thereby achieving the desired compressive strain for PFETs while maintaining device performance through proper material selection and deposition control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases tensile strain in NFETs and compressive strain in PFETs, leading to enhanced device performance and manufacturing efficiency without degrading thickness or increasing complexity.
Implementation Method 1
replacing SiGe interposers in NFET device regions with substantially pure Ge to enhance tensile strain
Implementation Method 2
replacing SiGe interposers in PFET device regions with dielectric materials to change tensile strain into neutral or compressive strain
Data Source
AI summary
A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.