Nanostructure FET Source/Drain Height Variation for Work Function Control

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, manufacturing challenges arise due to variations in source/drain region heights affecting channel regions and work functions, leading to pattern loading effects and reduced manufacturing yield.

Innovation Solution

The implementation of nanostructure-FETs with source/drain regions of varying heights, where some regions contact more adjacent nanostructures than others, allowing for controlled effective work functions and avoiding pattern loading effects by maintaining the same dimensions for nanostructures across different regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If source/drain regions are formed with varying heights to control effective work functions, then device performance and efficiency are balanced, but manufacturing complexity increases

Engineering Contradiction:
Improveeffective work function controlVSAvoidsource/drain region height variation
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by forming source/drain regions with different heights in different device regions. Specifically, first source/drain regions are formed with a first height while second source/drain regions are formed with a second height, allowing each region to have optimized electrical characteristics tailored to its specific functional requirements, thereby achieving controlled effective work functions across the device.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces height variation as an additional dimensional parameter for source/drain region formation. Instead of only varying lateral dimensions or doping concentrations, the invention utilizes the vertical dimension by forming source/drain regions at different heights, creating a three-dimensional structure that enables new degrees of freedom in work function control and device performance optimization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If feature sizes are reduced to improve integration density, then more components can be integrated, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidsource/drain region height control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the source/drain regions with specific height variations before subsequent processing steps. The different heights are established early in the fabrication sequence, allowing these structural differences to be maintained through subsequent processing and enabling precise control of effective work functions before final device assembly and testing.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If source/drain regions contact different quantities of nanostructures, then effective work functions are controlled, but device uniformity decreases

Engineering Contradiction:
Improveeffective work function controlVSAvoiddevice uniformity
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by allowing different source/drain regions to contact different quantities of nanostructures based on their specific functional requirements. First source/drain regions contact a first quantity of nanostructures while second source/drain regions contact a second quantity, enabling localized optimization of effective work functions while maintaining overall device functionality through controlled variability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20230420520A1Transistor Source/Drain Regions and Methods of Forming the Same
Publication Date: 2023.12.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230420520A1 patent drawing
  • US20230420520A1 patent drawing
  • US20230420520A1 patent drawing

AI summary

In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.