Nanostructure Gate Stack With Dielectric Barrier for p-FET Integrity
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining the integrity and performance of transistor structures, particularly in nanostructure-FETs, due to the need for precise processing that avoids damage to gate dielectric layers and improves integration density.
Innovation Solution
A protection layer is applied during annealing to modify the work function of the underlying gate dielectric layer, followed by an oxygen-containing etchant to form a dielectric barrier layer, which protects the work function tuning layer and enhances the performance of p-type devices by preventing damage during subsequent processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but the gate dielectric layer becomes more susceptible to damage during processing
Solution Approach 1:
A protection layer is deposited over the work function tuning layer before annealing processing. This preliminary protective action prevents direct exposure of the gate dielectric layer to high-temperature annealing, thereby maintaining its integrity while enabling the necessary processing for improved integration density
Solution Approach 2:
The protection layer acts as an intermediary between the annealing process and the gate dielectric layer. It mediates the thermal processing by absorbing or distributing the thermal stress, allowing the work function tuning layer to be modified without directly exposing the gate dielectric layer to damaging conditions
2Reliability
If annealing is performed to modify the work function of the gate dielectric layer, then the performance of p-type devices is improved, but the gate dielectric layer may be damaged during the process
Solution Approach 1:
The protection layer is deposited in advance before the annealing process. This preliminary protective measure ensures that when annealing is performed to improve device performance, the gate dielectric layer is already shielded from potential thermal damage
Solution Approach 2:
The annealing process, which could potentially harm the gate dielectric layer, is converted into a beneficial process by using the protection layer to selectively modify the work function of the gate dielectric layer through the work function tuning layer, while preventing direct damage
3Manufacturing precision
If the work function tuning layer is exposed during annealing, then direct modification is achieved, but damage to the underlying gate dielectric layer occurs
Solution Approach 1:
The protection layer is selectively positioned over the work function tuning layer, allowing local modification of the gate dielectric layer's work function through the tuning layer while protecting other areas. This enables precise work function modification without widespread damage to the gate dielectric layer
Solution Approach 2:
The protection layer serves as a localized intermediary that enables precise thermal coupling between the annealing process and the work function tuning layer, achieving manufacturing precision in work function modification while preventing damage to the gate dielectric layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach helps maintain the integrity of gate dielectric layers in p-type regions, improving the performance of nanostructure-FETs by avoiding damage and enhancing operational efficiency.
Implementation Method 1
The protection layer protects the underlying work function tuning layer during the annealing process
Implementation Method 2
The protection layer is removed with an oxygen-containing etchant, which promotes formation of a dielectric barrier layer on the work function tuning layer
Implementation Method 3
An annealing process is subsequently performed to modify the work function of an underlying gate dielectric layer
Data Source
AI summary
In an embodiment, a device includes: a first nanostructure; a gate dielectric layer around the first nanostructure; a first p-type work function tuning layer on the gate dielectric layer; a dielectric barrier layer on the first p-type work function tuning layer; and a second p-type work function tuning layer on the dielectric barrier layer, the dielectric barrier layer being thinner than the first p-type work function tuning layer and the second p-type work function tuning layer.