Nanostructure Gate Oxide Thickness Layout for Corner Breakdown
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining the integrity and reliability of gate oxides, particularly at the corners where electrical fields concentrate, leading to potential dielectric breakdown.
Innovation Solution
The formation of gate oxides in nanostructure transistors is optimized by making the vertical portions on the sidewalls thicker than the horizontal portions on the top and bottom surfaces, and further adjusting the process to increase the thickness of corner portions, thereby reducing electrical field concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate oxide thickness is reduced to accommodate smaller feature sizes, then the integration density is improved, but the reliability deteriorates due to dielectric breakdown at corners
Solution Approach 1:
The patent applies local quality by making the gate oxide thickness non-uniform: thicker at corners and sidewalls where electrical fields concentrate, and thinner at top and bottom surfaces. This localized variation in thickness allows the device to maintain high integration density while preventing dielectric breakdown at critical corner regions through increased oxide thickness and reduced electric field strength.
Solution Approach 2:
The patent introduces asymmetry in the gate oxide structure by creating different thicknesses at different locations (corners versus top/bottom surfaces). This asymmetric thickness distribution is specifically designed to address the non-uniform electrical field distribution in scaled devices, with thicker oxide at corners where field concentration causes reliability issues.
2Reliability
If the gate oxide thickness is increased at corners to prevent breakdown, then the reliability is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the non-uniform gate oxide structure before subsequent processing steps. The selective thickening of corner and sidewall regions is accomplished during the oxide formation process itself, preparing the structure in advance to handle electrical stress while maintaining compatibility with following manufacturing steps.
Solution Approach 2:
The patent changes the physical parameter of gate oxide thickness from a uniform value to a spatially varying value. By controlling the oxidation process parameters, the patent achieves different oxide thicknesses at different locations (thicker at corners, thinner at top/bottom), thereby improving reliability without requiring additional complex processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of dielectric breakdown by distributing the electrical stress more evenly across the gate oxide layers, while maintaining the necessary thickness for the horizontal portions to accommodate subsequent gate stack formations.
Implementation Method 1
oxidizing the plurality of semiconductor layers in the portion of the stack to form gate oxides on the plurality of semiconductor layers
Data Source
AI summary
A device includes a semiconductor nanostructure, and an oxide layer, which includes horizontal portions on a top surface and a bottom surface of the semiconductor nanostructure, vertical portions on sidewalls of the semiconductor nanostructure, and corner portions on corners of the semiconductor nanostructure. The horizontal portions have a first thickness. The vertical portions have a second thickness. The corner portions have a third thickness. Both of the second thickness and the third thickness are greater than the first thickness. A high-k dielectric layer surrounds the oxide layer. A gate electrode surrounds the high-k dielectric layer.