Nanostructure Gate Width Uniformity Through Differential Spacer Etching
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Solution Overview
Problem
Conventional fabrication techniques for field-effect transistors result in fin stacks with gate devices that are wider at the bottom than at the top, leading to suboptimal performance due to non-uniform gate width, which can cause instability in threshold voltage and device performance.
Innovation Solution
The method involves forming semiconductor fin stacks with alternating layers of varying semiconductor materials, such as silicon and silicon germanium, where lower layers have higher germanium concentration or greater thickness, allowing for controlled etching to achieve a uniform gate width by partially removing the sacrificial layers and filling with dielectric material, resulting in a gate device with consistent width across all layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication techniques are used to form fin stacks, then the gate device is formed, but the gate width becomes non-uniform (wider at bottom than top), leading to threshold voltage instability
Solution Approach 1:
The patent applies preliminary action by performing a lateral etch on the sacrificial semiconductor layers before forming the gate structure. This pre-processing step creates a uniform width profile in the remaining sacrificial layers, which then enables the formation of a gate device with uniform width. The lateral etch removes material laterally from the sacrificial layers at different rates depending on their position, pre-compensating for the non-uniformity that would otherwise occur during subsequent gate formation processes.
2Manufacturing precision
If alternating layers of varying semiconductor materials are used with different germanium concentrations, then controlled etching can achieve uniform gate width, but the fabrication process becomes more complex
Solution Approach 1:
The patent applies local quality by creating sacrificial semiconductor layers with spatially varying germanium concentrations. Each layer has a different material composition tailored to its specific position and function in the etching process. The lower sacrificial layers have higher germanium concentrations that etch faster, while upper layers have lower concentrations that etch slower, enabling differential lateral etching rates that compensate for the tapered geometry and achieve uniform gate width.
Solution Approach 2:
The patent applies parameter changes by systematically varying the germanium concentration parameter across different sacrificial layers. This material composition parameter is adjusted to control the etching rate parameter during lateral etching. By changing the germanium concentration from layer to layer, the process achieves differential etching behavior that transforms the initial non-uniform fin stack geometry into a uniform gate structure.
3Reliability
If the fin stack geometry is corrected to achieve uniform gate width, then device performance improves, but additional processing steps are required
Solution Approach 1:
The patent uses sacrificial semiconductor layers as intermediary structures that mediate between the initial non-uniform fin stack geometry and the desired uniform gate structure. These sacrificial layers with varying germanium concentrations serve as temporary structures that enable controlled lateral etching to achieve uniform geometry. After the gate is formed with the desired uniform width, the sacrificial layers are removed, having served their purpose as intermediaries in the fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a more uniform gate width, improving device performance by reducing variations in threshold voltage and enhancing the overall functionality of nanostructure devices like GAA FETs and FinFETs.
Implementation Method 1
lower layers have a higher doping concentration than upper layers... each layer of the first semiconductor material varies in characteristics that affect etch rate
Data Source
AI summary
According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.