Nanostructure Transistor Stacking for Variable Channel Widths
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Solution Overview
Problem
Existing integrated circuits face challenges in increasing computing power while maintaining area efficiency, as conventional transistors do not easily allow for variations in channel width without increasing substrate area.
Innovation Solution
The integration of nanostructure transistors with adjustable effective channel widths is achieved by stacking multiple nanostructures and controlling the connection of these nanostructures to the source/drain regions through epitaxial growth, allowing for varying channel widths without increasing substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional transistors are used to increase computing power, then the number of transistors can be increased, but the substrate area required increases proportionally
Solution Approach 1:
The patent transitions from planar transistor layouts to vertically stacked three-dimensional transistor structures. Multiple channel regions are stacked vertically above the substrate, allowing multiple transistors to occupy a smaller footprint area while maintaining electrical functionality. This vertical stacking enables increased transistor density without proportionally increasing substrate area.
Solution Approach 2:
The transistor channel region is divided into multiple discrete stacked segments or channel regions. Each channel region can be independently controlled via separate gate electrodes, allowing the transistor to function as multiple parallel channels. This segmentation increases effective channel width and computing capability within a compact vertical structure.
2Adaptability or versatility
If nanostructure transistors with varied channel widths are created, then device performance can be optimized, but design complexity increases
Solution Approach 1:
Different channel regions within the stacked transistor structure have different effective channel widths, allowing local optimization of device characteristics. By varying the width of individual channel regions, the transistor can provide different performance characteristics (e.g., high-speed vs. low-power) in different vertical segments while maintaining a unified structural framework.
Solution Approach 2:
The stacked transistor structure serves multiple functions simultaneously: it provides both high-speed performance through wider channel regions and low-power performance through narrower channel regions within the same device structure. This multi-functionality eliminates the need for separate transistor designs for different performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of transistors with specific performance characteristics, such as lower power consumption or higher speed, without increasing design complexity or substrate area, thereby improving device performance and wafer yield.
Implementation Method 1
controlling the connection of these nanostructures to the source/drain regions through epitaxial growth
Data Source
AI summary
An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.