Nanostructure Transistors With Dopant-Blocking Superlattice Offsets
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Solution Overview
Problem
Current semiconductor devices face limitations in enhancing charge carrier mobility and performance due to issues like alloy scattering, defect density, and sub-stoichiometric insulating properties at interfaces, which affect device efficiency and mobility.
Innovation Solution
The implementation of a semiconductor superlattice structure with alternating layers of silicon and non-semiconductor materials like oxygen, forming dopant blocking superlattices and buffer layers to reduce charged impurity concentration, improve interface quality, and enhance carrier confinement, thereby increasing mobility and providing piezoelectric and ferroelectric properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternating layers of silicon and non-semiconductor materials are deposited to form superlattice structures, then charge carrier mobility is improved and scattering effects are reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The silicon layer is segmented into alternating thin layers with non-semiconductor materials (oxygen, carbon, nitrogen) to create a superlattice structure. This segmentation reduces alloy scattering and improves charge carrier mobility by creating a periodic potential landscape that enhances carrier transport while maintaining structural order.
Solution Approach 2:
A composite material system is formed by combining silicon with non-semiconductor materials in alternating layers. The silicon provides the semiconductor functionality while the non-semiconductor layers provide scattering reduction and structural stabilization, creating a composite structure with superior electrical properties compared to pure silicon.
2Reliability
If superlattice structures with multiple alternating layers are formed, then interface quality and carrier confinement are improved, but manufacturing precision requirements increase
Solution Approach 1:
The non-semiconductor layers (oxygen, carbon, nitrogen) are deposited in advance as buffer layers before the main silicon layer deposition. This preliminary action prepares the interface by reducing defects and improving adhesion, ensuring high interface quality before the critical silicon layer formation begins.
Solution Approach 2:
The thickness of alternating layers is precisely controlled at the nanometer and sub-nanometer scale to achieve the desired superlattice periodicity. By adjusting layer thickness parameters, the electronic band structure is tuned to optimize carrier confinement and mobility while maintaining manufacturability through standard deposition techniques.
3Reliability
If dopant blocking superlattices are formed adjacent to nanostructures, then charged impurity concentration is reduced and mobility enhanced, but device fabrication complexity increases
Solution Approach 1:
The dopant blocking superlattice acts as an intermediary structure between the doped source/drain regions and the undoped silicon channel nanostructures. This intermediate layer prevents dopant diffusion into the channel while allowing electrical contact, effectively blocking charged impurities without requiring direct contact between source/drain and channel.
Solution Approach 2:
The dopant blocking superlattice is selectively formed only in specific regions adjacent to the silicon nanostructures where dopant diffusion needs to be prevented. The local quality of this region is enhanced with alternating layers to provide targeted dopant blocking, while other regions maintain standard silicon structure for optimal electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach leads to improved charge carrier mobility, reduced scattering effects, and enhanced device performance, including higher mobility and direct energy bandgap characteristics suitable for opto-electronic devices, while also acting as a barrier to dopant and material diffusion.
Implementation Method 1
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Implementation Method 2
Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility
Implementation Method 3
U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain
Implementation Method 4
forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions
Data Source
AI summary
A method for making semiconductor device may include forming spaced apart gate stacks on a substrate defining respective trenches therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, forming respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.