Nonvolatile Nanotube Diodes for High-Density Memory Arrays
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Solution Overview
Problem
The semiconductor industry faces challenges in developing denser memory technologies that reduce chip area while maintaining memory efficiency and cost-effectiveness, as existing solutions like 3-D EPROM arrays are limited to one-time programmable memories and require significant lithographic and process changes, which are not scalable for larger memory functions.
Innovation Solution
The development of nonvolatile nanotube diodes and nanotube blocks that utilize nanotube switching elements to create conductive pathways between terminals in response to electrical stimuli, enabling multiple logic states and scalable memory arrays with nanotube-based nonvolatile random access memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3-D EPROM arrays are used to achieve higher memory density, then memory capacity increases, but the technology is limited to one-time programmable memories and requires significant lithographic and process changes
Solution Approach 1:
The patent changes the fundamental operating parameter from one-time programming (antifuse breakdown) to multi-time programmable switching (nanotube resistance modulation). The nanotube switching element can be repeatedly switched between high and low resistance states, enabling multiple programming cycles and erasing operations, thus providing both high density and programming flexibility.
2Area of stationary object
If existing memory technologies are scaled down to reduce chip area, then memory density improves, but defect densities increase and process features become more difficult to control
Solution Approach 1:
The patent transitions from planar 2-D memory structures to vertically stacked 3-D nanotube devices. By stacking multiple memory cells vertically along the nanotube axis, the patent achieves higher density without further lateral scaling, thereby avoiding the defect density issues associated with continued miniaturization of lithographic features.
3Quantity of substance
If lithography technology is pushed to smaller line and spacing dimensions to increase memory density, then memory capacity increases, but alignment between layers becomes more difficult and manufacturing complexity increases
Solution Approach 1:
The patent employs vertical stacking of memory cells along the nanotube axis, achieving higher memory capacity through the third dimension rather than through lateral scaling. This approach eliminates the need for progressively smaller lithographic line and spacing dimensions, thereby maintaining alignment precision and reducing manufacturing complexity.
4Adaptability or versatility
If nanotube switching elements are used to create conductive pathways, then memory arrays become scalable and can be integrated on a single substrate, but device structure becomes more complex
Solution Approach 1:
The patent combines the nanotube switching element, semiconductor diode, and interconnect structures into an integrated vertical stack. This merging of components into a single vertically-aligned structure achieves scalability and substrate integration while actually reducing lateral footprint and simplifying the overall device architecture compared to traditional planar layouts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of high-density memory arrays that can write logic states multiple times, integrate on a single semiconductor substrate, and are scalable, addressing the limitations of existing technologies by reducing chip area and improving memory efficiency and cost-effectiveness.
Implementation Method 1
nanotube switching elements to create conductive pathways between terminals in response to electrical stimuli
Data Source
AI summary
A high-density memory array. A plurality of word lines and a plurality of bit lines are arranged to access a plurality of memory cells. Each memory cell includes a first conductive terminal and an article in physical and electrical contact with the first conductive terminal, the article comprising a plurality of nanoscopic particles. A second conductive terminal is in physical and electrical contact with the article. Select circuitry is arranged in electrical communication with a bit line of the plurality of bit lines and one of the first and second conductive terminals. The article has a physical dimension that defines a spacing between the first and second conductive terminals such that the nanotube article is interposed between the first and second conducive terminals. A logical state of each memory cell is selectable by activation only of the bit line and the word line connected to that memory cell.