Nanowire Capacitor Array Isolation for High Density and Low ESR
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Solution Overview
Problem
Existing nanowire-based capacitor structures face challenges in achieving high capacitance density and low Equivalent Series Resistance (ESR) due to limitations in porous anodic oxide thickness and lack of isolation between capacitors.
Innovation Solution
A method of manufacturing a multi-capacitor component using a nanowire structure, where islands of conductive material are formed on a substrate, a sacrificial layer is added between the islands, and anodization creates a porous anodic oxide template with nanowires extending from the conductive islands, allowing for electrical isolation between groups of nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a porous anodic oxide template is used to form nanowire structures, then capacitance density can be improved, but the Equivalent Series Resistance (ESR) increases due to limited template thickness
Solution Approach 1:
The patent divides the capacitor structure into multiple independent capacitor units, each with its own nanowire array. By segmenting the overall capacitor into separate units with individual current collectors, the patent enables thinner anodic oxide layers per unit while maintaining high total capacitance, thereby reducing ESR in each segment while preserving overall capacitance density.
Solution Approach 2:
The patent transitions from a planar capacitor structure to a three-dimensional nanowire array structure. By growing nanowires vertically from the substrate surface, the patent increases the effective surface area for capacitance storage without increasing the planar footprint, enabling high capacitance density with thinner oxide layers and reduced ESR.
2Productivity
If multiple capacitors are integrated into a single component, then productivity is improved, but electrical isolation between capacitors becomes difficult to achieve
Solution Approach 1:
The patent divides the integrated capacitor component into multiple independent capacitor units, each with its own isolated current collector and nanowire array. This segmentation enables electrical isolation between capacitors while maintaining high integration density, as each unit can be independently formed and isolated without affecting others.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures during fabrication. These sacrificial layers are positioned between adjacent capacitor units and are selectively removed to create electrical isolation. The sacrificial layers serve as temporary mediators that enable both high integration during fabrication and subsequent electrical isolation between completed capacitor units.
3Ease of manufacture
If a common current collector is used for multiple capacitors, then ease of manufacture is improved, but mechanical strength and uniformity of electrode layers deteriorate
Solution Approach 1:
The patent divides the current collector into multiple separate, isolated current collectors, each supporting its own nanowire array and capacitor structure. This segmentation improves mechanical strength by providing dedicated support for each capacitor unit and ensures uniform electrode layer formation, as each current collector can be independently processed without being constrained by a large common structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of a monolithic capacitor array with isolated capacitors, improving capacitance density and reducing ESR, while also enhancing mechanical strength and uniformity of electrode and insulator layers.
Implementation Method 1
anodizing the anodizable layer to form a porous anodic oxide template
Data Source
AI summary
A nanowire structure is manufactured by forming islands of conductive material on a substrate, and a conductive sacrificial layer in the space between conductive islands. The conductive islands include an anodic etch barrier layer. An anodizable layer is formed, over the conductive islands and sacrificial layer, and anodized to form a porous template. Nanowires are formed in regions of the porous template that overlie the conductive islands. Removal of the porous template and sacrificial layer leaves a nanowire structure including isolated groups of nanowires connected to respective conductive islands which function as current collectors. Respective stacks of conductive and insulator layers are formed over different groups of the nanowires to form respective capacitors that are electrically isolated from one another. A monolithic component may thus be formed including an array of isolated capacitors formed over nanowires.