Nanowire FET Work Function Engineering via Pitch-Proportional Deposition
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Solution Overview
Problem
Current nanowire field-effect transistor (FET) devices face challenges in implementing multiple threshold voltage (Vt) devices due to random dopant fluctuation effects and process complexity, especially as nanowire diameter is scaled, and engineering different work functions for various Vt's requires substantial process complexity.
Innovation Solution
The technique involves using a work function setting material deposited in amounts proportional to the nanowire pitch, forming gate stacks with a conformal first gate material and interfacial oxide, allowing for the modulation of threshold voltages by varying the volume of the work function setting material based on nanowire pitch, enabling the fabrication of multiple Vt devices without complex doping or different work function gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If doping is used to implement multiple threshold voltage devices, then multiple Vt devices can be achieved, but random dopant fluctuation effects occur and reliability deteriorates as nanowire diameter is scaled
Solution Approach 1:
The patent changes the parameter of work function by depositing different amounts of work function setting material (such as titanium nitride or tantalum nitride) in the gate stack. By controlling the thickness or volume of this material layer, different threshold voltages are achieved without doping, thereby avoiding random dopant fluctuation effects while maintaining multiple Vt device capability
Solution Approach 2:
The patent replaces the doping mechanism (introducing impurity atoms) with a physical deposition mechanism (depositing work function setting material). This substitution eliminates the statistical fluctuations inherent in doping while providing controlled threshold voltage adjustment through material thickness control
2Adaptability or versatility
If gate stacks with different work functions are engineered for different Vt's, then multiple threshold voltage devices can be achieved, but process complexity increases substantially
Solution Approach 1:
The patent applies local quality by depositing work function setting material with spatial variation - the amount of material is controlled based on local nanowire pitch. Regions with different pitch values receive different amounts of work function setting material, creating locally optimized threshold voltages without requiring globally different gate stack processes
Solution Approach 2:
The patent introduces dynamics by making the work function adjustable through a continuous parameter (material thickness/volume) rather than discrete gate stack designs. This allows flexible threshold voltage tuning across different nanowire pitch regions using a single dynamic deposition process
3Volume of moving object
If nanowire diameter is scaled for further miniaturization, then device density increases, but random dopant fluctuation effects become extremely problematic
Solution Approach 1:
The patent replaces doping with work function engineering through material deposition. This substitution is particularly effective for scaled nanowires where doping becomes unreliable, as the deposited material layer thickness can be precisely controlled even for very small nanowire diameters, maintaining reliability while enabling further scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous fabrication of multiple threshold voltage nanowire FET devices by modulating the work function setting material volume with nanowire pitch, reducing process complexity and avoiding random dopant fluctuation issues, while maintaining a simplified fabrication process.
Implementation Method 1
A work function setting material is deposited on the conformal first gate material, at least partially surrounding the nanowires
Data Source
AI summary
A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.