Nanowire Transistor Gate Dielectric Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The downscaling of semiconductor devices has led to a short channel effect in transistors, reducing their reliability, and existing multi-gate structures face challenges in optimizing performance due to parasitic capacitance and crystal quality issues in nanowire transistors.
Innovation Solution
A semiconductor device with a nanowire transistor configuration that includes a first transistor with an inner-insulating spacer between the gate dielectric layer and the source/drain region to reduce parasitic capacitance, and a second transistor with a gate dielectric layer extending between the gate electrode and the source/drain region to enhance crystal quality, thereby improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nanowire transistors are used to reduce short channel effect, then transistor reliability is improved, but parasitic capacitance increases and crystal quality deteriorates
Solution Approach 1:
The gate dielectric layer is segmented into two distinct structures: a first gate dielectric layer that is spaced from the source/drain region using an inner-insulating spacer, and a second gate dielectric layer that extends to and contacts the source/drain region. This segmentation allows different portions of the gate dielectric to serve different functions, reducing parasitic capacitance while maintaining crystal quality.
Solution Approach 2:
Different regions of the gate dielectric structure are assigned different properties: the first gate dielectric layer region is designed with spacing from the source/drain region to minimize parasitic capacitance effects, while the second gate dielectric layer region is designed to contact the source/drain region to maintain crystal quality and reduce defects. This local differentiation resolves the contradiction between reducing parasitic capacitance and maintaining crystal quality.
2Stability of the object's composition
If gate dielectric layer contacts source/drain region to enhance crystal quality, then crystal quality is improved, but parasitic capacitance increases
Solution Approach 1:
The gate dielectric layer is divided into two segments with different contact configurations to the source/drain region. The first gate dielectric layer is spaced from the source/drain region by an inner-insulating spacer to reduce parasitic capacitance, while the second gate dielectric layer contacts the source/drain region to enhance crystal quality. This segmentation enables simultaneous optimization of both parameters.
Solution Approach 2:
Different local regions of the gate dielectric structure have different contact characteristics: one region is spaced from the source/drain region to minimize parasitic capacitance, while another region contacts the source/drain region to maximize crystal quality. This local quality differentiation resolves the contradiction between reducing parasitic capacitance and enhancing crystal quality.
3Object-generated harmful factors
If inner-insulating spacer is added to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The gate dielectric layer is segmented into two parts, with the first portion spaced from the source/drain region using an inner-insulating spacer to reduce parasitic capacitance. While this adds structural elements, the segmentation enables precise control over electric field distribution and parasitic capacitance reduction.
Solution Approach 2:
An inner-insulating spacer is introduced as an intermediary element between the first gate dielectric layer and the source/drain region. This spacer serves as a mediator to reduce parasitic capacitance while maintaining the beneficial effects of the gate dielectric structure on crystal quality.
Data Source
AI summary
A semiconductor device includes a first transistor in a first region of a substrate and a second transistor in a second region of the substrate. The first transistor includes multiple first semiconductor patterns; a first gate electrode; a first gate dielectric layer; a first source/drain region; and an inner-insulating spacer. The second transistor includes multiple second semiconductor patterns; a second gate electrode; a second gate dielectric layer; and a second source/drain region. The second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region. The first source/drain region is not in contact with the first gate dielectric layer.