Nanowire Gate Layout for Wider Channels Under Gate-Cut Constraints
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the trade-off between the smallest dimension of a feature patterned in a semiconductor stack and the spacing between such features, particularly in multi-gate transistors like tri-gate transistors, which limits the ribbon width and affects performance due to constraints imposed by gate cuts and endcaps.
Innovation Solution
Implementing extreme ultraviolet (EUV) direct ribbon patterning to allow flexible placement of ribbons, increasing ribbon width in areas without gate cuts and maintaining continuity where the gate is uncut, thereby optimizing ribbon size and spacing for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern features in a semiconductor stack, then the critical dimension can be reduced, but the spacing between features must be increased
Solution Approach 1:
The patent introduces gate cuts that extend vertically through the gate structure, adding a third dimension (depth) to the patterning approach. This vertical gating allows horizontal spacing between ribbons to be reduced while maintaining electrical isolation, effectively decoupling the critical dimension control from the spacing requirement that would normally exist in planar lithography
Solution Approach 2:
The gate structure is segmented into discrete regions through gate cuts, creating isolated gate sections over different ribbon groups. This segmentation allows independent optimization of ribbon width and spacing in different regions, enabling tighter overall packing while maintaining proper electrical isolation where needed
2Length of moving object
If gate cuts are implemented to provide electrical isolation, then spacing between ribbons can be reduced, but ribbon width is limited
Solution Approach 1:
Gate cuts are applied selectively in specific regions rather than uniformly across the entire structure. This allows ribbon width to be maximized in regions where gate cuts are not needed, while still providing electrical isolation where gate cuts are implemented, creating a locally optimized structure that balances both requirements
3Power
If ribbon width is increased to improve drive current, then performance improves, but spacing requirements increase
Solution Approach 1:
By introducing vertical gate cuts, the patent enables ribbon width to be increased in the horizontal plane without proportionally increasing spacing requirements, as the vertical isolation provided by gate cuts compensates for the reduced horizontal spacing that would normally be required
Data Source
AI summary
A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.