Nanowire Gate Stack Formation via Selective High-k Deposition
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Solution Overview
Problem
Maintaining device performance and good short channel control becomes challenging beyond the 14 nm technology node in semiconductor manufacturing, necessitating new materials and integration schemes such as nanowire devices for improved mobility and scaling.
Innovation Solution
A method for forming nanowire devices involves providing a substrate with nanowires between vertical spacers, selectively depositing a high-k film and a metal-containing gate electrode layer on the nanowires, with optional dielectric material deposition to control gate-to-drain capacitance and using self-assembled monolayers to block deposition on spacers, enabling precise control of the gate stack formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling is used beyond 14 nm node, then device density increases, but device performance and short channel control deteriorate
Solution Approach 1:
The patent transitions from planar 2D device structures to three-dimensional nanowire structures with vertical channels. This dimensional change enables continued scaling and increased device density while maintaining effective gate control through the wrap-around gate configuration that surrounds the nanowire channel in multiple directions, addressing short channel control issues that arise at advanced technology nodes
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and integrates nanowire channels made from various semiconductor materials (Si, Ge, III-V compounds) with different spacer and insulation materials. This composite approach enables optimized electrical performance and short channel control at sub-14 nm nodes while maintaining manufacturability
2Productivity
If spacer thickness is reduced for further scaling, then device density increases, but manufacturing precision and deposition control become more challenging
Solution Approach 1:
The patent forms sacrificial mandrel structures and preliminary spacer layers before final nanowire formation and gate stack deposition. These preliminary structures serve as templates that define the final spacer dimensions and positions, enabling precise control of thin spacer thicknesses through self-aligned processes that reduce variability and improve manufacturing precision at scaled dimensions
Solution Approach 2:
The patent introduces intermediate sacrificial mandrels and temporary spacer materials that facilitate the formation of final thin spacers. These intermediary structures enable indirect formation of precise spacer geometries through sequential deposition and removal steps, allowing better control over final spacer thickness and uniformity than direct deposition methods
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device mobility, reduces leakage current, and maintains performance by allowing for thin spacers and optimized gate stack formation, addressing the challenges of scaling and short channel control beyond the 14 nm node.
Implementation Method 1
selectively depositing a high-k film on the nanowires relative to the vertical spacers
Implementation Method 2
using self-assembled monolayers to block deposition on spacers
Data Source
AI summary
A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.


