Nanowire Internal Spacer Formation via Selective Etching
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Solution Overview
Problem
The formation of internal spacers in nanowire semiconductor devices is process and material intensive, and existing methods fail to effectively reduce parasitic capacitance due to overlap between the gate and source-drain region of transistors.
Innovation Solution
A method involving the formation of a stack of sacrificial and nanowire materials, selective removal of sacrificial material to create recesses, deposition of dielectric material, and subsequent etching to form gaps, allowing for the growth of electrode material that merges to create an internal spacer with a low k-value, such as an air gap, between nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If internal spacer formation is implemented to reduce parasitic capacitance, then parasitic capacitance is reduced, but the process becomes more complex and material intensive
Solution Approach 1:
The internal spacer formation process is divided into multiple sequential steps: forming recesses in sacrificial material, depositing dielectric material in recesses, selectively removing excess dielectric material, and forming gaps. This segmentation allows each step to be optimized independently and enables the complex process to be managed through modular operations.
Solution Approach 2:
Dielectric material is deposited into the recesses formed in the sacrificial material before the final gap formation step. This preliminary action ensures that the dielectric material is already in position when the gaps are created, eliminating the need for subsequent dielectric deposition steps and reducing overall process complexity.
2Reliability
If dielectric material is deposited conformally to fill recesses, then dielectric coverage is improved, but material usage increases and excess dielectric must be removed
Solution Approach 1:
The dielectric material is deposited conformally only in the recessed regions where it is needed, rather than uniformly across the entire surface. This local quality approach ensures adequate dielectric coverage in critical areas while minimizing excess material deposition elsewhere, reducing waste and subsequent removal requirements.
Solution Approach 2:
Excess dielectric material that is deposited beyond the recess regions is selectively removed through etching processes. This extraction step eliminates unnecessary material while preserving the dielectric material that is properly positioned within the recesses, thereby reducing material waste and preparing the structure for gap formation.
3Object-affected harmful factors
If gaps are enlarged to form internal spacers, then parasitic capacitance is reduced, but dielectric coverage may be compromised
Solution Approach 1:
The gaps are enlarged to a degree that is sufficient to reduce parasitic capacitance but controlled to maintain adequate dielectric coverage. The etching process is optimized to create gaps of appropriate size without completely removing the dielectric material, achieving the right balance between capacitance reduction and structural integrity.
Solution Approach 2:
The size and shape of the gaps are precisely controlled by adjusting etching parameters such as etchant concentration, temperature, and exposure time. These parameter changes enable the formation of gaps that are large enough to reduce parasitic capacitance while maintaining sufficient dielectric material coverage to ensure device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces parasitic capacitance by creating a low k-value internal spacer with a gap, enhancing the integration of nanowires and reducing defects, while maintaining sufficient dielectric coverage for selective etching and nanowire release.
Implementation Method 1
The excess dielectric material can be removed using a first etch process without enlarging the crevice
Implementation Method 2
a second etch process is used for enlarging the crevice. This process can be selected such that it etches more efficiently in the crevice than the first etch process
Implementation Method 3
growing electrode material on the outer ends of the nanowire material such that the electrode material growing from neighboring outer ends merges, thereby covering the gap
Data Source
AI summary
A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.